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290645-24 march 2008 numonyx? advanced+ boot block flash memory (c3) 28f800c3, 28f160c3, 28f320c3 (x16) datasheet product features ? flexible smartvoltage technology ? 2.7 v? 3.6 v read/program/erase ? 12 v for fast production programming ? 1.65 v to 2.5 v or 2.7 v to 3.6 v i/o option ? reduces overall system power ? high performance ? 2.7 v? 3.6 v: 70 ns max access time ? optimized architecture for code plus data storage ? eight 4 kword blocks, top or bottom parameter boot ? up to 127 x 32 kword blocks ? fast program suspend capability ? fast erase suspend capability ? flexible block locking ? lock/unlock any block ? full protection on power-up ? write protect (wp#) pin for hardware block protection ? low power consumption ?9 ma typical read ? 7 ua typical standby with automatic power savings feature ? extended temperature operation ? -40 c to +85 c ? 128-bit protection register ? 64 bit unique device identifier ? 64 bit user programmable otp cells ? extended cycling capability ? minimum 100,000 block erase cycles ? software ? supported by numonyx advanced flash file managers -- numonyx? vfm, numonyx? fdi, etc. ? code and data storage in the same memory device ? robust power loss recovery for data loss prevention ? common flash interface ? standard surface mount packaging ? 48-ball bga*/vfbga ? 64-ball easy bga packages ?48-tsop package ? intel etox* viii (0.13 m ) flash technology ? 8, 16, 32 mbit ? intel etox* vii (0.18 m ) flash technology ? 16, 32 mbit ? intel etox* vi (0.25 m ) flash technology ? 8, 16 and 32 mbit
datasheet march 2008 2 290645-24 legal lines and disclaimers information in this document is provided in connection with numo nyx? products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in numonyx's terms and conditions of sale for such products, numonyx assumes no liability whatsoever, and numonyx disclaims any express or implied warranty, relating to sale and/or use of numonyx products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. numonyx products are not intended for use in medical, life saving, life sustaining, critical co ntrol or safety systems, or in nuclear f acility applications. numonyx b.v. may make changes to specifications an d product descriptions at any time, without notice. numonyx b.v. may have patents or pending patent applications, tr ademarks, copyrights, or other intellectual property rights tha t relate to the presented subject matter. the furnishing of documents and other materials and information does not provide any license, express or implie d, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. designers must not rely on the absence or characteristics of any features or instructions marked ?reserved? or ?undefined.? num onyx reserves these for future definition and shall have no respon sibility whatsoever for conf licts or incompatibilities arising from future changes to them. contact your local numonyx sales office or your distributor to ob tain the latest specifications and before placing your product order. copies of documents which have an order number and are referenced in this document, or other numonyx literature may be obtained by visiting the numonyx website at http://www.numonyx.com . numonyx, the numonyx logo, and strataflash are trademarks or regist ered trademarks of numonyx b.v. or its subsidiaries in other countries. *other names and brands may be claimed as the property of others. copyright ? 2008, numonyx b.v., all rights reserved.
march 2008 datasheet 290645-24 3 c3 discrete contents 1.0 introduction .............................................................................................................. 7 1.1 nomenclature ..................................................................................................... 7 1.2 conventions ....................................................................................................... 8 2.0 functional overview .................................................................................................. 9 2.1 product overview ................................................................................................ 9 2.2 block diagram .................................................................................................. 10 2.3 memory map..................................................................................................... 10 3.0 package information ............................................................................................... 13 3.1 mbga* and vf bga package .............................................................................. 13 3.2 tsop package................................................................................................... 14 3.3 easy bga package............................................................................................. 15 4.0 ballout and signal descriptions ............................................................................... 16 4.1 48-lead tsop package ...................................................................................... 16 4.2 64-ball easy bga package .................................................................................. 19 4.3 signal descriptions ............................................................................................ 19 5.0 maximum ratings and operating conditions ............................................................ 21 5.1 absolute maximum ratings................................................................................. 21 5.2 operating conditions ......................................................................................... 21 6.0 electrical specifications ........................................................................................... 23 6.1 current characteristics.............................. ......................................................... 23 6.2 dc voltage characteristics........................... ....................................................... 24 7.0 ac characteristics ................................................................................................... 26 7.1 ac read characteristics ..................................................................................... 26 7.2 ac write characteristics ..................................................................................... 30 7.3 erase and program timings ................................................................................ 34 7.4 ac i/o test conditions....................................................................................... 34 7.5 device capacitance ........................................................................................... 35 8.0 power and reset specifications ............................................................................... 36 8.1 active power (program/erase/read) .................................................................... 36 8.2 automatic power savings (aps) .......................................................................... 36 8.3 standby power.................................................................................................. 36 8.4 deep power-down mode..................................................................................... 36 8.5 power and reset considerations .......................................................................... 37 8.5.1 power-up/down characteristics................................................................ 37 8.5.2 rp# connected to system reset .............................................................. 37 8.5.3 vcc, vpp and rp# transitions.................................................................. 37 8.5.4 reset specifications................................................................................ 37 8.6 power supply decoupling ................................................................................... 38 9.0 device operations ................................................................................................... 39 9.1 bus operations ................................................................................................. 39 9.1.1 read .................................................................................................... 39 9.1.2 write .................................................................................................... 39 9.1.3 output disable ....................................................................................... 39 9.1.4 standby ................................................................................................ 39 9.1.5 reset.................................................................................................... 40 10.0 modes of operation ................................................................................................. 41
c3 discrete datasheet march 2008 4 290645-24 10.1 read mode........................................................................................................41 10.1.1 read array ............................................................................................41 10.1.2 read identifier .......................................................................................41 10.1.3 cfi query ..............................................................................................42 10.1.4 read status register...............................................................................42 10.1.4.1 clear status register .................................................................43 10.2 program mode...................................................................................................43 10.2.1 12-volt production programming ..............................................................43 10.2.2 suspending and resuming program ..........................................................44 10.3 erase mode .......................................................................................................44 10.3.1 suspending and resuming erase ..............................................................44 11.0 security modes ........................................................................................................48 11.1 flexible block locking.........................................................................................48 11.1.1 locking operation...................................................................................48 11.1.1.1 locked state ............................................................................49 11.1.1.2 unlocked state .........................................................................49 11.1.1.3 lock-down state.......................................................................49 11.2 reading block-lock status ..................................................................................49 11.3 locking operations during erase suspend .............................................................49 11.4 status register error checking ............................................................................50 11.5 128-bit protection register .................................................................................50 11.5.1 reading the protection register ................................................................50 11.5.2 programming the protection register......... ................................................51 11.5.3 locking the protection register............... ..................................................51 11.6 v pp program and erase voltages ..........................................................................51 11.6.1 program protection .................................................................................51
march 2008 datasheet 290645-24 5 c3 discrete revision history date of revision version description 05/12/98 -001 original version 07/21/98 -002 48-lead tsop package diagram change bga package diagrams change 32-mbit ordering information change (section 6) cfi query structure output table change (table c2) cfi primary-vendor specific extended query table change for optional features and command support change (table c8) protection register address change i ppd test conditions clarification (section 4.3) bga package top side mark information clarification (section 6) 10/03/98 -003 byte-wide protection register address change v ih specification chan ge (section 4.3) v il maximum specification change (section 4.3) i ccs test conditions clarification (section 4.3) added command sequence error note (table 7) datasheet renamed from 3 volt advanced boot block, 8-, 16-, 32-mbit flash memory family. 12/04/98 -004 added t bhwh /t bheh and t qvbl (section 4.6) programming the protection register clarification (section 3.4.2) 12/31/98 -005 removed all references to x8 configurations 02/24/99 -006 removed reference to 40-lead tsop from front page 06/10/99 -007 added easy bga package (section 1.2) removed 1.8 v i/o references locking operations flowchart changed (appendix b) added t whgl (section 4.6) cfi primary vendor-specific extended query changed (appendix c) 03/20/00 -008 max i ccd changed to 25 a table 10, added note indicating v cc max = 3.3 v for 32-mbit device 04/24/00 -009 added specifications for 0.18 micron product offerings throughout document added 64- mbit density 10/12/00 -010 changed references of 32mbit 80ns devices to 70ns devices to reflect the faster product offering. changed vccmax=3.3v reference to indicate that the affected product is the 0.25 m 32mbit device. minor text edits throughout document. 7/20/01 -011 added 1.8v i/o operation documentation where applicable added tsop pcn ?pin-1? indicator information changed references in 8 x 8 bga pino ut diagrams from ?gnd? to ?vssq? added ?vssq? to pin descriptions information removed 0.4 m references in dc characteristics table corrected 64mb package ordering info rmation from 48-ubga to 48-vfbga corrected ?bottom? parameter block size s to on 8mb device to 8 x 4kwords minor text edits throughout document 10/02/01 -012 added specifications for 0.13 micr on product offerings throughout document 2/05/02 -013 corrected iccw / ippw / icces /ippes values. added mechanicals for 16mb and 64mb minor text edits throughout document. 4/05/02 -014 updated 64mb product offerings. updated 16mb product offerings. revised and corrected dc characteristics table. added mechanicals for easy bga. minor text edits throughout document. 3/06/03 -016 complete technical update.
c3 discrete datasheet march 2008 6 290645-24 10/01/03 -017 corrected information in the device geometry details table, address 0x34. 5/20/04 -018 updated the layout of the datasheet. 9/1/04 -019 fixed typo for standby power on cover page. 9/14/04 -020 added lead-free line items to table 38, ?product information ordering matrix? on page 70 . 9/27/04 -021 added specification for 8mb 0.13 micron device. added 0.13 micron to table 38, ?product information ordering matrix? on page 70 . 1/26/05 -022 converted datasheet to new template. deleted description in table 4. deleted note in figure 5. 5/16/05 -023 removed all 64m ordering information, removed vf bga 8m ordering information. removed 64m reference in title page only. adde d software verbiage in title page. corrected lead width (b) measurement in fig 2., ubga and vf bga package drawing and dimensions, page 12. march 2008 24 applied numnyx branding. date of revision version description
march 2008 datasheet 290645-24 7 c3 discrete 1.0 introduction this datasheet contains the specifications for the numonyx? advanced+ boot block flash memory (c3) device family, hereafte r called the c3 flash memory device. these flash memories add features such as instant block locking and protection registers that can be used to enhance the security of systems. the numonyx? advanced+ book block flas h memory (c3) device, manufactured on intel?s latest 0.13 m and 0.18 m technologies, represents a feature-rich solution for low-power applications. the c3 device incorporates low-voltage capability (3 v read, program, and erase) with high-speed, low-power operation. flexible block locking allows any block to be independently lock ed or unlocked. add to this the numonyx? flash data integrator (numonyx? fdi) so ftware and you have a cost-effective, flexible, monolithic code plus data storage solution. numonyx? advanced+ boot block flash memory (c3) products are available in 48-lead tsop, 48-ball csp, and 64-ball easy bga packages. additional information on this product family can be obtained from the numonyx? flash website: http://www.numonyx.com 1.1 nomenclature 0x hexadecimal prefix 0b binary prefix byte 8 bits word 16 bits kw or kword 1024 words mword 1,048,576 words kb 1024 bits kb 1024 bytes mb 1,048,576 bits mb 1,048,576 bytes aps automatic power savings csp chip scale package cui command user interface otp one time programmable pr protection register prd protection register data plr protection lock register rfu reserved for future use sr status register srd status register data wsm write state machine
c3 discrete datasheet march 2008 8 290645-24 1.2 conventions the terms pin and signal are often used interc hangeably to refer to the external signal connections on the package; for chip scale package (csp) the term ball is used. group membership brackets: square brackets will be used to designate group membership or to define a group of signals with similar function (i.e. a[21:1], sr[4:1]) set : when referring to registers, the term set means the bit is a logical 1. clear: when referring to registers, the term clear means the bit is a logical 0. block: a group of bits (or words) that erase simultaneously with one block erase instruction. main block : a block that contains 32 kwords. parameter block : a block that contains 4 kwords.
march 2008 datasheet 290645-24 9 c3 discrete 2.0 functional overview this section provides an overview of the numonyx? advanced+ boot block flash memory (c3) device features and architecture. 2.1 product overview the c3 flash memory device provides high-performance asynchronous reads in package-compatible densities with a 16 bit data bus. individually-erasable memory blocks are optimally sized for code and data storage. eight 4 kword parameter blocks are located in the boot block at either the top or bottom of the device?s memory map. the rest of the memory array is grouped into 32 kword main blocks. the device supports read-array mode operations at various i/o voltages (1.8 v and 3 v) and erase and program operations at 3 v or 12 v vpp. with the 3 v i/o option, vcc and vpp can be tied together for a simple, ultra-low-power design. in addition to i/o voltage flexibility, the dedicated vpp input pr ovides complete data protection when v pp v pplk . the c3 discrete device features a 128-bit protection register enabling security techniques and data protection schemes through a combination of factory-programmed and user-programmable otp data registers. zero-latency locking/unlocking on any memory block provides instant and complete protection for critical system code and data. additional block lock-down capability provides hardware protection where software commands alone cannot change the block?s protection status. a command user interface (cui) serves as the interface between the system processor and internal operation of the device. a valid command sequence issued to the cui initiates device automation . an internal write state machine (wsm) automatically executes the algorithms and timings necessary for block erase, program, and lock-bit configuration operations. the device offers three low-power saving features: automatic power savings (aps), standby mode, and deep power-down mode . the device automa tically enters aps mode following read cycle completion. standby mode begins when the system deselects the flash memory by deasserting chip enable, ce#. the deep power-down mode begins when reset deep power-down , rp# is asserted, which deselects the memory and places the outputs in a high-impedance state, producing ultra-low power savings. combined, these three power-savings features significantly enhanced power consumption flexibility.
c3 discrete datasheet march 2008 10 290645-24 2.2 block diagram 2.3 memory map the c3 discrete device is asymmetrically bl ocked, which enables system code and data integration within a single flash device. the bulk of the array is divided into 32 kword main blocks that can store code or data, and 4 kword boot blocks to facilitate storage of boot code or for frequently changing small parameters. see table 1, ?top boot memory map? on page 11 and table 2, ?bottom boot memory map? on page 12 for details. figure 1: c3 flash memory device block diagram output m ult i ple xer 4-kword para mete r b loc k 32- kw ord main block 32- kw ord main block 4-kword para mete r b loc k y-g at ing/ sensing w rit e st at e machine program/ erase volt age swit ch dat a comparat or st at us regist er i dent if ier regist er da ta re gi st er i / o logic address lat ch address count er x-decoder y-decoder power reduct ion cont rol i nput buf f er output buffer gnd v cc v pp ce# we# oe# rp# command user interface i nput buf f er dq 0 -dq 15 v ccq wp# a[max:min]
march 2008 datasheet 290645-24 11 c3 discrete table 1: top boot memory map size (kw ) blk 8-mbit memory addressin g (hex) size (kw ) blk 16-mbit memory addressing (hex) size (kw ) blk 32-mbit memory addressin g (hex) size (kw ) blk 64-mbit memory addressing (hex) 422 7f000- 7ffff 4 38 ff000-fffff 470 1ff000- 1fffff 4 134 3ff000-3fffff 421 7e000- 7efff 4 37 fe000-fefff 469 1fe000- 1fefff 4 133 3fe000-3fefff 420 7d000- 7dfff 4 36 fd000-fdfff 468 1fd000- 1fdfff 4 132 3fd000-3fdfff 419 7c000- 7cfff 4 35 fc000-fcfff 467 1fc000- 1fcfff 4 131 3fc000-3fcfff 418 7b000- 7bfff 4 34 fb000-fbfff 466 1fb000- 1fbfff 4 130 3fb000-3fbfff 417 7a000- 7afff 4 33 fa000-fafff 465 1fa000- 1fafff 4 129 3fa000-3fafff 416 79000- 79fff 4 32 f9000-f9fff 464 1f9000- 1f9fff 4 128 3f9000-3f9fff 415 78000- 78fff 4 31 f8000-f8fff 463 1f8000- 1f8fff 4 127 3f8000-3f8fff 32 14 70000- 77fff 32 30 f0000-f7fff 32 62 1f0000- 1f7fff 32 126 3f0000-3f7fff 32 13 68000- 6ffff 32 29 e8000-effff 32 61 1e8000- 1effff 32 125 3e8000-3effff 32 12 60000- 67fff 32 28 e0000-e7fff 32 60 1e0000- 1e7fff 32 124 3e0000-3e7fff 32 11 58000- 5ffff 32 27 d8000-dffff 32 59 1d8000- 1dffff 32 123 3d8000-3dffff ... ... ... ... ... ... ... ... ... ... ... ... 32 2 10000- 17fff 32 2 10000-17fff 32 2 10000- 17fff 32 2 10000-17fff 32 1 8000-0ffff 32 1 08000-0ffff 32 1 08000- 0ffff 32 1 08000-0ffff 32 0 0000-07fff 32 0 00000-07fff 32 0 00000- 07fff 32 0 00000-07fff
c3 discrete datasheet march 2008 12 290645-24 table 2: bottom boot memory map size (kw ) blk 8-mbit memory addressin g (hex) size (kw ) blk 16-mbit memory addressing (hex) size (kw ) blk 32-mbit memory addressing (hex) size (kw ) blk 64-mbit memory addressing (hex) 32 22 78000- 7ffff 32 38 f8000-fffff 32 70 1f8000- 1fffff 32 134 3f8000-3fffff 32 21 70000- 77fff 32 37 f0000-f7fff 32 69 1f0000- 1f7fff 32 133 3f0000-3f7fff 32 20 68000- 6ffff 32 36 e8000-effff 32 68 1e8000- 1effff 32 132 3e8000-3effff 32 19 60000- 67fff 32 35 e0000-e7fff 32 67 1e0000- 1e7fff 32 131 3e0000-3e7fff ... ... ... ... ... ... ... ... ... . ... ... 32 10 18000- 1ffff 32 10 18000-1ffff 32 10 18000-1ffff 32 10 18000-1ffff 32 9 10000- 17fff 32 9 10000-17fff 32 9 10000-17fff 32 9 10000-17fff 32 8 08000- 0ffff 32 8 08000-0ffff 32 8 08000-0ffff 32 8 08000-0ffff 47 07000- 07fff 4 7 07000-07fff 4 7 07000-07fff 4 7 07000-07fff 46 06000- 06fff 4 6 06000-06fff 4 6 06000-06fff 4 6 06000-06fff 45 05000- 05fff 4 5 05000-05fff 4 5 05000-05fff 4 5 05000-05fff 44 04000- 04fff 4 4 04000-04fff 4 4 04000-04fff 4 4 04000-04fff 43 03000- 03fff 4 3 03000-03fff 4 3 03000-03fff 4 3 03000-03fff 42 02000- 02fff 4 2 02000-02fff 4 2 02000-02fff 4 2 02000-02fff 41 01000- 01fff 4 1 01000-01fff 4 1 01000-01fff 4 1 01000-01fff 40 00000- 00fff 4 0 00000-00fff 4 0 00000-00fff 4 0 00000-00fff
march 2008 datasheet 290645-24 13 c3 discrete 3.0 package information 3.1 bga* and vf bga package figure 2: bga* and vf bga packag e drawing and dimensions bottom view -bump side up e b s1 ball a1 corner top view - bump side down ball a1 corner e d side view a a2 a 1 seating y a b c d e f s2 plan 1 2 3 4 5 6 7 8 a b c d e f 123 4 5678 note: drawing not to scale millimeters inches dimensions symbol min nom max min nom max package height a 1.000 0.0394 ball height a1 0.150 0.0059 package body thickness a2 0.665 0.0262 ball (lead) width b 0.325 0.375 0.425 0.0128 0.0148 0.0167 package body length 8m (.25) d 7.810 7.910 8.010 package body length 16m (.25/.18/.13) 32m (.25/.18/.13) d 7.186 7.286 7.386 0.2829 0.2868 0.2908 package body length 64m (.18) d 7.600 7.700 7.800 0.2992 0.3031 0.3071 package body width 8m (.25) e 6.400 6.500 6.600 0.2520 0.2559 0.2598 package body width 16m (.25/.18/.13) 32m (.18/.13) e 6.864 6.964 7.064 0.2702 0.2742 0.2781 package body width 32m (.25) e 10.750 10.850 10.860 0.4232 0.4272 0.4276 package body width 64m (.18) e 8.900 9.000 9.100 0.3504 0.3543 0.3583 pitch e 0.750 0.0295 ball (lead) count 8m, 16m n 46 46 ball (lead) count 32m n 47 47 ball (lead) count 64m n 48 48 seating plane coplanarity y 0.100 0.0039 corner to ball a1 distance along d 8m (.25) s1 1.230 1.330 1.430 0.0484 0.0524 0.0563 corner to ball a1 distance along d 16m (.25/.18/.13) 32m (.18/.13) s1 0.918 1.018 1.118 0.0361 0.0401 0.0440 corner to ball a1 distance along d 64m (.18) s1 1.125 1.225 1.325 0.0443 0.0482 0.0522 corner to ball a1 distance along e 8m (.25) s2 1.275 1.375 1.475 0.0502 0.0541 0.0581 corner to ball a1 distance along e 16m (.25/.18/.13) 32m (.18/.13) s2 1.507 1.607 1.707 0.0593 0.0633 0.0672 corner to ball a1 distance along e 32m (.25) s2 3.450 3.550 3.650 0.1358 0.1398 0.1437 corner to ball a1 distance along e 64m (.18) s2 2.525 2.625 2.725 0.0994 0.1033 0.1073 c3 discrete 8/16/32/64m, .25,.18, .13u ubga/vfbga r0
c3 discrete datasheet march 2008 14 290645-24 3.2 tsop package notes: 1. one dimple on package denotes pin 1. 2. if two dimples, then the larger dimple denotes pin 1. 3. pin 1 will always be in the upper left corner of the package, in refere nce to the product mark. figure 3: tsop package drawing and dimensions a 0 l detail a y d c z pin 1 e d 1 b detail b see detail a e se e d e ta il b a 1 a 2 se a tin g plane see not es 1, 2, 3 and 4 table 3: tsop package dimensions parameter symbol millimeters inches min nom max min nom max package height a 1.200 0.047 standoff a1 0.050 0.002 package body thickness a2 0 .950 1.000 1.050 0.037 0.039 0.041 lead width b 0.150 0.200 0.300 0.006 0.008 0.012 lead thickness c 0.100 0.150 0.200 0.004 0.006 0.008 package body length d1 18. 200 18.400 18.600 0.717 0.724 0.732 package body width e 11.800 12.000 12.200 0.465 0.472 0.480 lead pitch e 0.500 0.0197 terminal dimension d 19.800 20.000 20.200 0.780 0.787 0.795 lead tip length l 0.500 0.600 0.700 0.020 0.024 0.028 lead count n 48 48 lead tip angle 0 3 5 0 3 5 seating plane coplanarity y 0.100 0.004 lead to package offset z 0 .150 0.250 0.350 0.006 0.010 0.014
march 2008 datasheet 290645-24 15 c3 discrete 3.3 easy bga package figure 4: easy bga packag e drawing and dimension millimeters inches symbol min nom max notes min nom max package height a 1.200 0.0472 ball height a 1 0.250 0.0098 package body thickness a 2 0.780 0.0307 ball (lead) width b 0.330 0.430 0.530 0.0130 0.0169 0.0209 package body width d 9.900 10.000 10.100 1 0.3898 0.3937 0.3976 package body length e 12.900 13.000 13.100 1 0.5079 0.5118 0.5157 pitch [e] 1.000 0.0394 ball (lead) count n 64 64 seating plane coplanarity y 0.100 0.0039 corner to ball a1 distance along d s 1 1.400 1.500 1.600 1 0.0551 0.0591 0.0630 corner to ball a1 distance along e s 2 2.900 3.000 3.100 1 0.1142 0.1181 0.1220 dimensions table note: (1) package dimensions are for reference only. these dimensions are estimates based on die size, and are subject to change. e seating plane s1 s2 e top view - ball side down bottom view - ball side up y a a1 d ball a1 corner a2 note: drawing not to scale a b c d e f g h 8 7654321 8 7 6 5 4 3 2 1 a b c d e f g h b ball a1 corner side view
c3 discrete datasheet march 2008 16 290645-24 4.0 ballout and signal descriptions the c3 device is available in 48-lead tsop, 48-ball vf bga, 48-ball bga, and easy bga packages. see figure 5 on page 16 , figure 7 on page 18 , and figure 8 on page 19 , respectively. 4.1 48-lead tsop package figure 5: 48-lead tsop package advanced+ boot block 48-lead tsop 12 mm x 20 mm top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 a 16 v ccq gnd dq 15 dq 7 dq 14 dq 6 dq 13 dq 5 dq 12 dq 4 v cc dq 11 dq 3 dq 10 dq 2 dq 9 dq 1 dq 8 dq 0 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 a 15 a 14 a 13 a 12 a 11 a 10 a 9 a 8 a 21 a 20 we# rp# v pp wp# a 19 a 18 a 17 a 7 a 6 a 5 21 22 23 24 oe# gnd ce# a 0 28 27 26 25 a 4 a 3 a 2 a 1 32 m 16 m 64 m
march 2008 datasheet 290645-24 17 c3 discrete figure 6: mark for pin-1 indicator on 48-lead 8-mb, 16-mb and 32-mb tsop note: the topside marking on 8 mb, 16 mb, and 32 mb numonyx? advanced and advanced + boot block 48l tsop products will convert to a white ink triangle as a pin 1 indicator. products without the white triangle will continue to use a dimple as a pin 1 indicator. there are no other changes in package size, materials, functionality, customer handling, or manufacturability. product will co ntinue to meet numonyx stringent quality requirements. products affected are numonyx ordering codes shown in ta b l e 4 . table 4: 48-lead tsop extended 64 mbit extended 32 mbit extended 16 mbit extended te28f320c3td70 te28f320c3bd70 te28f160c3td70 te28f160c3bd70 te28f800c3ta90 te28f800c3ba90 te28f320c3tc70 te28f320c3bc70 te28f160c3tc80 te28f160c3bc80 te28f800c3ta110 te28f800c3ba110 te28f320c3tc90 te28f320c3bc90 te28f160c3ta90 te28f160c3ba90 te28f320c3ta100 te28f320c3ba100 te28f160c3ta110 te28f160c3ba110 te28f320c3ta110 te28f320c3ba110 current mark: new mark:
c3 discrete datasheet march 2008 18 290645-24 notes: 1. shaded connections indicate the upgrade address connectio ns. numonyx recommends to not use routing in this area. 2. a19 denotes 16 mbit; a20 denotes 32 mbit; a21 denotes 64 mbit. 3. unused address balls are not populated. figure 7: 48-ball bga* and 48-ball vf bga chip scale package (top view, ball down) 1,2,3 13 25 47 68 a b c d e f a13 a14 a15 a16 v ccq a11 a10 a12 d14 d15 a8 we# a9 d5 d6 vpp rp# a21 d11 d12 wp# a18 a20 d2 d3 a19 a17 a6 d8 d9 a7 a5 a3 ce# d0 a4 a2 a1 a0 gnd gnd d7 d13 d4 vcc d10 d1 oe# 16m 32m 64m
march 2008 datasheet 290645-24 19 c3 discrete 4.2 64-ball easy bga package figure 8: 64-ball easy bga package 1,2 notes: 1. a19 denotes 16 mbit; a20 denotes 32 mbit; a21 denotes 64 mbit. 2. unused address balls are not populated. 4.3 signal descriptions table 5: signal descriptions symbol type description a[max:0] input address inputs for memory addresses. address are internally latched during a program or erase cycle. 8 mbit: amax= a18 16 mbit: amax = a19 32 mbit: amax = a20 64 mbit: amax = a21 dq[15:0] input/ output data inputs/outputs: inputs data and commands during a write cycle; outputs data during read cycles. inputs commands to the command user in terface when ce# and we# are active. data is internally latched. the data pins float to tri-stat e when the chip is de-sel ected or the outputs are disabled. ce# input chip enable: active-low input. activates the internal co ntrol logic, input buffers, decoders and sense amplifiers. ce# is active low. ce # high de-selects the memory device and reduces power consumption to standby levels. oe# input output enable: active-low input. enables the device?s outputs through the data buffers during a read operation. rp# input reset/deep power-down: active-low input. when rp# is at logic low, the device is in reset/ deep power-down mode, which drives the outputs to high-z, resets the write state machine, and minimizes current levels (i ccd ). when rp# is at logic high, the devi ce is in standard operation. when rp# transitions from logic-low to logic-high, the device resets all blocks to locked and defaults to the read array mode. 1 2 3 4 5 6 7 8 a b c d e f g h top view - ball side bottom view - ball side a 1 a 6 a 18 v pp v cc gnd a 10 a 15 a 2 a 17 a 19 (1) rp# du a 20 (1) a 11 a 14 a 3 a 7 wp# we# du a 21 (1) a 12 a 13 a 4 a 5 du dq 8 dq 1 dq 9 dq 3 dq 12 dq 6 du du ce# dq 0 dq 10 dq 11 dq 5 dq 14 du du a 0 v ssq dq 2 dq 4 dq 13 dq 15 v ssq a 16 a 22 (2) oe# v ccq v cc v ssq dq 7 v ccq du du du du a 8 a 9 8 7 6 5 4 3 2 1 a b c d e f g h a 15 a 10 gnd v cc v pp a 18 a 6 a 1 a 14 a 11 a 20 (1) du rp# a 19 (1) a 17 a 2 a 13 a 12 a 21 (1) du we# wp# a 7 a 3 a 9 a 8 du du du dq 6 dq 12 dq 3 dq 9 dq 1 dq 8 du du dq 14 dq 5 dq 11 dq 10 dq 0 ce# a 16 v ssq d 15 d 13 dq 4 dq 2 v ssq a 0 du v ccq d 7 v ssq v cc v ccq oe# a 22 (2) du du du a 5 a 4
c3 discrete datasheet march 2008 20 290645-24 we# input write enable: active-low input. we# controls writes to the device. address and data are latched on the rising edge of the we# pulse. wp# input write protect: active-low input. when wp# is a logic low, the lock -down mechanism is enabled and blocks marked lock-down cannot be unlocked through software. when wp# is logic high, the lock-d own mechanism is disabled and blocks previously locked-down are now locked and can be unlocked and locked through software. after wp# goes low, any blocks previously marked lock-down revert to the lock-down state. see section 11.0, ?security modes? on page 48 for details on block locking. vpp input/ power program/erase power supply: operates as an input at logic levels to control complete device protection. supplies power for accelerate d program and erase operations in 12 v 5% range. do not leave this pin floating. lower vpp vpplk to protect all contents against program and erase commands. set vpp = vcc for in-system read, program and erase operations. in this configuration, vpp can drop as low as 1.65 v to allow for resistor or diode drop from the system supply. apply vpp to 12 v 5% for faster program and erase in a production environment. applying 12 v 5% to vpp can only be done for a maximum of 1000 cycl es on the main blocks and 2500 cycles on the boot blocks. vpp can be connected to 12 v for a total of 80 hours maximum. see section 11.6 for details on vpp voltage configurations. vcc power device core power supply: supplies power for device operations. vccq power output power supply: output-driven source voltage. this ball can be tied directly to v cc if operating within v cc range. gnd power ground: for all internal circuitry. all ground inputs must be connected. du ? do not use: do not use this ball. this ball must not be connected to any power supplies, signals or other balls,; it must be left floating. nc ? no connect table 5: signal descriptions symbol type description
march 2008 datasheet 290645-24 21 c3 discrete 5.0 maximum ratings and operating conditions 5.1 absolute maximum ratings warning: stressing the device beyond the ?absolut e maximum ratings? may cause permanent damage. these ratings are stress ratings only. operation beyond the ?operating conditions? is not recommended, and exte nded exposure beyond the ?operating conditions? may affect device reliability. . 5.2 operating conditions notice: specifications are subject to change without notice. verify with your local numonyx sales office that you have the latest datasheet before finalizing a design. parameter maximum rating notes extended operating temperature during read ?40 c to +85 c during block erase and program ?40 c to +85 c temperature under bias ?40 c to +85 c storage temperature ?65 c to +125 c voltage on any pin (except v cc and v pp ) with respect to gnd ?0.5 v to +3.7 v 1 v pp voltage (for block erase and program) wi th respect to gnd ?0.5 v to +13.5 v 1,2,3 v cc and v ccq supply voltage with respec t to gnd ?0.2 v to +3.6 v output short circuit current 100 ma 4 notes: 1. minimum dc voltage is ?0.5 v on input/output pins. du ring transitions, this level may undershoot to ?2.0 v for periods <20 ns. maximum dc voltage on input/output pins is v cc +0.5 v which, during transitions, may overshoot to v cc +2.0 v for periods <20 ns. 2. maximum dc voltage on v pp may overshoot to +14.0 v for periods <20 ns. 3. v pp program voltage is normally 1.65 v?3.6 v. connec tion to a 11.4 v?12.6 v supply can be done for a maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks during program/ erase. v pp may be connected to 12 v for a total of 80 hours maximum. 4. output shorted for no more th an one second. no more than one output shorted at a time. table 6: temperature and vo ltage operating conditions symbol parameter notes min max units t a operating temperature ?40 +85 c v cc1 v cc supply voltage 1, 2 2.7 3.6 volts v cc2 1, 2 3.0 3.6 v ccq1 i/o supply voltage 12.73.6 volts v ccq2 1.65 2.5 v ccq3 1.8 2.5 v pp1 supply voltage 1 1.65 3.6 volts
c3 discrete datasheet march 2008 22 290645-24 v pp2 1, 3 11.4 12.6 volts cycling block erase cycling 3 100,000 cycles notes: 1. v cc and v ccq must share the same supply when they are in the v cc1 range. 2. v cc max = 3.3 v for 0.25 m 32-mbit devices. 3. applying v pp = 11.4 v?12.6 v during a program/erase can only be done for a maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks. v pp may be connected to 12 v for a total of 80 hours maximum. table 6: temperature and vo ltage operating conditions symbol parameter notes min max units
march 2008 datasheet 290645-24 23 c3 discrete 6.0 electrical specifications 6.1 current characteristics table 7: dc current charac teristics (she et 1 of 2) sym parameter v cc 2.7 v?3.6 v 2.7 v?2.85 v 2.7 v?3.3 v unit test conditions v ccq 2.7 v?3.6 v 1.65 v?2.5 v 1.8 v?2.5 v note typ max typ max typ max i li input load current 1,2 1 1 1a v cc = v cc max v ccq = v ccq max v in = v ccq or gnd i lo output leakage current 1,2 10 10 10 a v cc = v cc max v ccq = v ccq max v in = v ccq or gnd i ccs v cc standby current for 0.13 and 0.18 micron product 1 7 15 20 50 150 250 a v cc = v cc max ce# = rp# = v ccq or during program/ erase suspend wp# = v ccq or gnd v cc standby current for 0.25 micron product 1 10 25 20 50 150 250 a i ccd v cc power-down current for 0.13 and 0.18 micron product 1,2 7 15 7 20 7 20 a v cc = v cc max v ccq = v ccq max v in = v ccq or gnd rp# = gnd 0.2 v v cc power-down current for 0.25 product 1,2 7 25 7 25 7 25 a i ccr v cc read current for 0.13 and 0.18 micron product 1,2,3 9 18 8 15 9 15 ma v cc = v cc max v ccq = v ccq max oe# = v ih , ce# =v il f = 5 mhz, i out =0 ma inputs = v il or v ih v cc read current for 0.25 micron product 1,2,3 10 18 8 15 9 15 ma i ppd v pp deep power-down current 1 0.2 5 0.2 5 0.2 5 a rp# = gnd 0.2 v v pp v cc i ccw v cc program current 1,4 18 55 18 55 18 55 ma v pp =v pp1, program in progress 82210 30 1030ma v pp = v pp2 (12v) program in progress i cce v cc erase current 1,4 16 45 21 45 21 45 ma v pp = v pp1, erase in progress 81516 45 1645ma v pp = v pp2 (12v) , erase in progress i cces / i ccws v cc erase suspend current for 0.13 and 0.18 micron product 1,4,5 7 15 50 200 50 200 a ce# = v ih, erase suspend in progress v cc erase suspend current for 0.25 micron product 10 25 50 200 50 200 a i ppr v pp read current 1,4 2 15 2 15 2 15 a v pp v cc 50 200 50 200 50 200 a v pp > v cc
c3 discrete datasheet march 2008 24 290645-24 6.2 dc voltage characteristics i ppw v pp program current 1,4 0.05 0.1 0.05 0.1 0.05 0.1 ma v pp =v pp1, program in progress 822 8 22 8 22ma v pp = v pp2 (12v) program in progress i ppe v pp erase current 1,4 0.05 0.1 0.05 0.1 0.05 0.1 ma v pp = v pp1, erase in progress 82216 45 1645ma v pp = v pp2 (12v) , erase in progress i ppes / i ppws v cc erase suspend current 1,4 0.2 5 0.2 5 0.2 5 a v pp = v pp1, program or erase suspend in progress 50 200 50 200 50 200 a v pp = v pp2 (12v) , program or erase suspend in progress notes: 1. all currents are in rms unless otherwise noted. typical values at nominal v cc , t a = +25 c. 2. the test conditions v cc max, v ccq max, v cc min, and v ccq min refer to the maximum or minimum v cc or v ccq voltage listed at the top of each column. v cc max = 3.3 v for 0.25 m 32-mbit devices. 3. automatic power savings (aps) reduces i ccr to approximately standby levels in static operat ion (cmos inputs). 4. sampled, not 100% tested. 5. i cces or i ccws is specified with device de-selected. if device is read while in erase suspend, current draw is sum of i cces and i ccr . if the device is read while in progra m suspend, current draw is the sum of i ccws and i ccr . table 8: dc voltage characteristics (sheet 1 of 2) sym parameter v cc 2.7 v?3.6 v 2.7 v?2.85 v 2.7 v?3.3 v unit test conditions v ccq 2.7 v?3.6 v 1.65 v?2.5 v 1.8 v?2.5 v note min max min max min max v il input low voltage ?0.4 v cc * 0.22 v ?0.4 0.4 ?0.4 0.4 v v ih input high voltage 2.0 v ccq +0.3v v ccq ? 0.4v v ccq +0.3v v ccq ? 0.4v v ccq +0.3v v v ol output low voltage ?0.1 0.1 -0.1 0.1 -0.1 0.1 v v cc = v cc min v ccq = v ccq min i ol = 100 a v oh output high voltage v ccq ?0.1v v ccq ? 0.1v v ccq ? 0.1v v v cc = v cc min v ccq = v ccq min i oh = ?100 a v pplk v pp lock- out voltage 1 1.0 1.0 1.0 v complete write protection v pp1 v pp during program / erase operations 1 1.65 3.6 1.65 3.6 1.65 3.6 v v pp2 1,2 11.4 12.6 11.4 12.6 11.4 12.6 v table 7: dc current characteristics (sheet 2 of 2) sym parameter v cc 2.7 v?3.6 v 2.7 v?2.85 v 2.7 v?3.3 v unit test conditions v ccq 2.7 v?3.6 v 1.65 v?2.5 v 1.8 v?2.5 v note typ max typ max typ max
march 2008 datasheet 290645-24 25 c3 discrete v lko v cc prog/ erase lock voltage 1.5 1.5 1.5 v v lko2 v ccq prog/ erase lock voltage 1.2 1.2 1.2 v notes: 1. erase and program are inhibited when v pp < v pplk and not guaranteed outside the valid v pp ranges of v pp1 and v pp2 . 2. applying v pp = 11.4 v?12.6 v during program/erase can only be done for a maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks. v pp may be connected to 12 v for a total of 80 hours maximum. table 8: dc voltage charac teristics (she et 2 of 2) sym parameter v cc 2.7 v?3.6 v 2.7 v?2.85 v 2.7 v?3.3 v unit test conditions v ccq 2.7 v?3.6 v 1.65 v?2.5 v 1.8 v?2.5 v note min max min max min max v il input low voltage ?0.4 v cc * 0.22 v ?0.4 0.4 ?0.4 0.4 v v ih input high voltage 2.0 v ccq +0.3v v ccq ? 0.4v v ccq +0.3v v ccq ? 0.4v v ccq +0.3v v v ol output low voltage ?0.1 0.1 -0.1 0.1 -0.1 0.1 v v cc = v cc min v ccq = v ccq min i ol = 100 a
c3 discrete datasheet march 2008 26 290645-24 7.0 ac characteristics 7.1 ac read characteristics table 9: read operations?8-mbit density #sym paramete r density 8 mbit product 70 ns 90 ns 110 ns v cc 2.7 v ? 3.6 v 3.0 v ? 3.6 v 2.7 v ? 3.6 v 3.0 v ? 3.6 v 2.7 v ? 3.6 v note min (ns) max (ns) min (ns) max (ns) min (ns) max (ns) min (ns) max (ns) min (ns) max (ns) r1 t avav read cycle time 3,4 70 80 90 100 110 r2 t avqv address to output delay 3,4 70 80 90 100 110 r3 t elqv ce# to output delay 1,3,4 70 80 90 100 110 r4 t glqv oe# to output delay 1,3,4 20 30 30 30 30 r5 t phqv rp# to output delay 3,4 150 150 150 150 150 r6 t elqx ce# to output in low z 2,3,4 0 0 0 0 0 r7 t glqx oe# to output in low z 2,3,4 0 0 0 0 0 r8 t ehqz ce# to output in high z 2,3,4 20 20 20 20 20 r9 t ghqz oe# to output in high z 2,3,4 20 20 20 20 20 r10 t oh output hold from address, ce#, or oe# change, whichever occurs first 2,3,4 0 0 0 0 0 notes: 1. oe# may be delayed up to t elqv? t glqv after the falling edge of ce# without impact on t elqv . 2. sampled, but not 100% tested. 3. see figure 9, ?read operation waveform? on page 29 . 4. see figure 11, ?ac input/output reference waveform? on page 34 for timing measurements and maximum allowable input slew rate.
march 2008 datasheet 290645-24 27 c3 discrete table 10: read operations?16-mbit density #sym paramet er densit y 16 mbit note s produ ct 70 ns 80 ns 90 ns 110 ns v cc 2.7 v?3.6 v 2.7 v?3.6 v 3.0 v?3.6 v 2.7 v?3.6 v 3.0 v? 3.6v 2.7 v? 3.6v min (ns) max (ns) min (ns) max (ns) min (ns) max (ns) min (ns) max (ns) min (ns ) ma x (ns ) min (ns ) ma x (ns ) r1 t avav read cycle time 70 80 80 90 100 110 3,4 r2 t avqv address to output delay 70 80 80 90 100 110 3,4 r3 t elqv ce# to output delay 70 80 80 90 100 110 1,3,4 r4 t glqv oe# to output delay 20 20 30 30 30 30 1,3,4 r5 t phqv rp# to output delay 150 150 150 150 150 150 3,4 r6 t elqx ce# to output in low z 0 0 0 0 0 0 2,3,4 r7 t glqx oe# to output in low z 0 0 0 0 0 0 2,3,4 r8 t ehqz ce# to output in high z 20 20 20 20 20 20 2,3,4 r9 t ghqz oe# to output in high z 20 20 20 20 20 20 2,3,4 r10 t oh output hold from address, ce#, or oe# change, whichever occurs first 0 0 0 0 0 0 2,3,4 notes: 1. oe# may be delayed up to t elqv? t glqv after the falling edge of ce# without impact on t elqv . 2. sampled, but not 100% tested. 3. see figure 9, ?read operation waveform? on page 29 . 4. see figure 11, ?ac input/output reference waveform? on page 34 for timing measurements and maximum allowable input slew rate.
c3 discrete datasheet march 2008 28 290645-24 table 11: read operations?32-mbit density #sym paramet er densit y 32 mbit note s produc t 70 ns 90 ns 100 ns 110 ns v cc 2.7 v?3.6 v 2.7 v?3.6 v 3.0 v?3.3 v 2.7 v?3.3 v 3.0 v?3.3 v 2.7 v?3.3 v min (ns) max (ns) min (ns) max (ns) min (ns) max (ns) min (ns) max (ns) min (ns ) max (ns ) min (ns) max (ns) r1 t avav read cycle time 70 90 90 100 100 110 3,4 r2 t avqv address to output delay 70 90 90 100 100 110 3,4 r3 t elqv ce# to output delay 70 90 90 100 100 110 1,3,4 r4 t glqv oe# to output delay 20 20 30 30 30 30 1,3,4 r5 t phqv rp# to output delay 150 150 150 150 150 150 3,4 r6 t elqx ce# to output in low z 0 0 0 0 0 0 2,3,4 r7 t glqx oe# to output in low z 0 0 0 0 0 0 2,3,4 r8 t ehqz ce# to output in high z 20 20 20 20 20 20 2,3,4 r9 t ghqz oe# to output in high z 20 20 20 20 20 20 2,3,4 r10 t oh output hold from address, ce#, or oe# change, whichever occurs first 0 0 0 0 0 0 2,3,4 notes: 1. oe# may be delayed up to t elqv? t glqv after the falling edge of ce# without impact on t elqv . 2. sampled, but not 100% tested. 3. see figure 9, ?read operation waveform? on page 29 . 4. see figure 11, ?ac input/output reference waveform? on page 34 for timing measurements and maximum allowable input slew rate.
march 2008 datasheet 290645-24 29 c3 discrete table 12: read operations ? 64-mbit density #sym parameter density 64 mbit unit product 70 ns 80 ns v cc 2.7 v?3.6 v 2.7 v?3.6 v note minmaxminmax r1 t avav read cycle time 3,4 70 80 ns r2 t avqv address to output delay 3,4 70 80 ns r3 t elqv ce# to output delay 1,3,4 70 80 ns r4 t glqv oe# to output delay 1,3,4 20 20 ns r5 t phqv rp# to output delay 3,4 150 150 ns r6 t elqx ce# to output in low z 2,3,4 0 0 ns r7 t glqx oe# to output in low z 2,3,4 0 0 ns r8 t ehqz ce# to output in high z 2,3,4 20 20 ns r9 t ghqz oe# to output in high z 2,3,4 20 20 ns r10 t oh output hold from address, ce#, or oe# change, whichever occurs first 2,3,4 0 0 ns notes: 1. oe# may be delayed up to t elqv? t glqv after the falling edge of ce# without impact on t elqv . 2. sampled, but not 100% tested. 3. see figure 9, ?read operation waveform? on page 29 . 4. see figure 11, ?ac input/output reference waveform? on page 34 for timing measurements and maximum allowable input slew rate. figure 9: read operation waveform r5 r10 r7 r6 r9 r4 r8 r3 r1 r2 r1 a ddress [a] ce# [e] oe# [g] we# [w] data [d/q] rst # [p]
c3 discrete datasheet march 2008 30 290645-24 7.2 ac write characteristics table 13: write operations?8-mbit density #sym parameter density 8 mbit product 70ns 90 ns 110 ns v cc 3.0 v ? 3.6 v 80 100 2.7 v ? 3.6 v 70 90 110 note min (ns) min (ns) min (ns) min (ns) min (ns) w1 t phwl / t phel rp# high recovery to we# (ce#) going low 4,5 150 150 150 150 150 w2 t elwl / t wlel ce# (we#) setup to we# (ce#) going low4,500000 w3 t wlwh / t eleh we# (ce#) pulse width 4,5 45 50 60 70 70 w4 t dvwh / t dveh data setup to we# (ce#) going high 2,4,54050506060 w5 t avwh / t aveh address setup to we# (ce#) going high 2,4,55050607070 w6 t wheh / t ehwh ce# (we#) hold time from we# (ce#) high4,500000 w7 t whdx / t ehdx data hold time from we# (ce#) high 2,4,500000 w8 t whax / t ehax address hold time from we# (ce#) high2,4,500000 w9 t whwl / t ehel we# (ce#) pulse width high 2,4,52530303030 w10 t vpwh / t vpeh v pp setup to we# (ce#) going high 3,4,5 200 200 200 200 200 w11 t qvvl v pp hold from valid srd 3,400000 w12 t bhwh / t bheh wp# setup to we# (ce#) going high 3,400000 w13 t qvbl wp# hold from valid srd 3,400000 w14 t whgl we# high to oe# going low 3,4 30 30 30 30 30 notes: 1. write pulse width (t wp ) is defined from ce# or we# goin g low (whichever goes low last) to ce# or we# going high (whichever goes high first). hence, t wp =t wlwh =t eleh =t wleh =t elwh . similarly, write pulse width high (t wph ) is defined from ce# or we# going high (whichever goes high first) to ce# or we# going low (w hichever goes low last). hence, t wph =t whwl =t ehel =t whel =t ehwl . 2. refer to table 23, ?command bus operations? on page 45 for valid a in or d in . 3. sampled, but not 100% tested. 4. see figure 11, ?ac input/output reference waveform? on page 34 for timing measurements and maximum allowable input slew rate. 5. see figure 10, ?write operations waveform? on page 33 .
march 2008 datasheet 290645-24 31 c3 discrete table 14: write operations?16-mbit density #symparameter density 16 mbit unit product 70 ns 80 ns 90 ns 110 ns v cc 3.0 v ? 3.6 v 80 100 2.7 v ? 3.6 v 70 80 90 110 not e min min min min min min w1 t phwl / t phel rp# high recovery to we# (ce#) going low 4,5 150 150 150 150 150 150 ns w2 t elwl / t wlel ce# (we#) setup to we# (ce#) going low 4,5 0 0 0 0 0 0 ns w3 t wlwh / t eleh we# (ce#) pulse width 1,4, 5 45 50 50 60 70 70 ns w4 t dvwh / t dveh data setup to we# (ce#) going high 2,4, 5 40 40 50 50 60 60 ns w5 t avwh / t aveh address setup to we# (ce#) going high 2,4, 5 50 50 50 60 70 70 ns w6 t wheh / t ehwh ce# (we#) hold time from we# (ce#) high 4,5 0 0 0 0 0 0 ns w7 t whdx / t ehdx data hold time from we# (ce#) high 2,4, 5 000000ns w8 t whax / t ehax address hold time from we# (ce#) high 2,4, 5 000000ns w9 t whwl / t ehel we# (ce#) pulse width high 1,4, 5 25 30 30 30 30 30 ns w10 t vpwh / t vpeh v pp setup to we# (ce#) going high 3,4, 5 200 200 200 200 200 200 ns w11 t qvvl v pp hold from valid srd 3,4 0 0 0 0 0 0 ns w12 t bhwh / t bheh wp# setup to we# (ce#) going high 3,4 0 0 0 0 0 0 ns w13 t qvbl wp# hold from valid srd 3,4 0 0 0 0 0 0 ns w14 t whgl we# high to oe# going low 3,4 30 30 30 30 30 30 ns notes: 1. write pulse width (t wp ) is defined from ce# or we# goin g low (whichever goes low last) to ce# or we # going high (whichever goes high first). hence, t wp =t wlwh =t eleh =t wleh =t elwh . similarly, write pulse width high (t wph ) is defined from ce# or we# going high (whichever goes high first) to ce# or we# going low (w hichever goes low last). hence, t wph =t whwl =t ehel =t whel =t ehwl . 2. refer to table 23, ?command bus operations? on page 45 for valid a in or d in . 3. sampled, but not 100% tested. 4. see figure 11, ?ac input/output reference waveform? on page 34 for timing measurements and maximum allowable input slew rate. 5. see figure 10, ?write operations waveform? on page 33 .
c3 discrete datasheet march 2008 32 290645-24 table 15: write operations?32-mbit density #sym parameter density 32 mbit unit product 70 ns 90 ns 100 ns 110 ns v cc 3.0 v ? 3.6 v 6 90 100 2.7 v ? 3.6 v 70 90 100 110 note min min min min min min w1 t phwl / t phel rp# high recovery to we# (ce#) going low 4,5 150 150 150 150 150 150 ns w2 t elwl / t wlel ce# (we#) setup to we# (ce#) going low 4,5 0 0 0 0 0 0 ns w3 t wlwh / t eleh we# (ce#) pulse width 1,4,5 45 60 60 70 70 70 ns w4 t dvwh / t dveh data setup to we# (ce#) going high 2,4,5 40 40 50 60 60 60 ns w5 t avwh / t aveh address setup to we# (ce#) going high 2,4,5 50 60 60 70 70 70 ns w6 t wheh / t ehwh ce# (we#) hold time from we# (ce#) high 4,5 0 0 0 0 0 0 ns w7 t whdx / t ehdx data hold time from we# (ce#) high 2,4,5 0 0 0 0 0 0 ns w8 t whax / t ehax address hold time from we# (ce#) high 2,4,5 0 0 0 0 0 0 ns w9 t whwl / t ehel we# (ce#) pulse width high 1,4,5 25 30 30 30 30 30 ns w10 t vpwh / t vpeh v pp setup to we# (ce#) going high 3,4,5 200 200 200 200 200 200 ns w11 t qvvl v pp hold from valid srd 3,4 0 0 0 0 0 0 ns w12 t bhwh / t bheh wp# setup to we# (ce#) going high 3,4 0 0 0 0 0 0 ns w13 t qvbl wp# hold from valid srd 3,4 0 0 0 0 0 0 ns w14 t whgl we# high to oe# going low 3,4 30 30 30 30 30 30 ns notes: 1. write pulse width (t wp ) is defined from ce# or we# goin g low (whichever goes low last) to ce# or we# going high (whichever goes high first). hence, t wp =t wlwh =t eleh =t wleh =t elwh . similarly, write pulse width high (t wph ) is defined from ce# or we# going high (whichever goes high first) to ce# or we# going low (w hichever goes low last). hence, t wph =t whwl =t ehel =t whel =t ehwl . 2. refer to table 23, ?command bus operations? on page 45 for valid a in or d in . 3. sampled, but not 100% tested. 4. see figure 11, ?ac input/output reference waveform? on page 34 for timing measurements and maximum allowable input slew rate. 5. see figure 10, ?write operations waveform? on page 33 . 6. v cc max = 3.3 v for 32-mbit 0.25 micron product.
march 2008 datasheet 290645-24 33 c3 discrete table 16: write operations?64-mbit density # symbol parameter density 64 mbit unit product 80 ns v cc 2.7 v ? 3.6 v note min w1 t phwl / t phel rp# high recovery to we# (ce#) going low 4,5 150 ns w2 t elwl / t wlel ce# (we#) setup to we# (ce#) going low 4,5 0 ns w3 t wlwh / t eleh we# (ce#) pulse width 1,4,5 60 ns w4 t dvwh / t dveh data setup to we# (ce#) going high 2,4,5 40 ns w5 t avwh / t aveh address setup to we# (ce#) going high 2,4,5 60 ns w6 t wheh / t ehwh ce# (we#) hold time from we# (ce#) high 4,5 0 ns w7 t whdx / t ehdx data hold time from we# (ce#) high 2,4,5 0 ns w8 t whax / t ehax address hold time from we# (ce#) high 2,4,5 0 ns w9 t whwl / t ehel we# (ce#) pulse width high 1,4,5 30 ns w10 t vpwh / t vpeh v pp setup to we# (ce#) going high 3,4,5 200 ns w11 t qvvl v pp hold from valid srd 3,4 0 ns w12 t bhwh / t bheh wp# setup to we# (ce#) going high 3,4 0 ns w13 t qvbl wp# hold from valid srd 3,4 0 ns w14 t whgl we# high to oe# going low 3,4 30 ns notes: 1. write pulse width (t wp ) is defined from ce# or we# goin g low (whichever goes low last) to ce# or we # going high (whichever goes high first). hence, t wp =t wlwh =t eleh =t wleh =t elwh . similarly, write pulse width high (t wph ) is defined from ce# or we# going high (whichever goes high first) to ce# or we# going low (w hichever goes low last). hence, t wph =t whwl =t ehel =t whel =t ehwl . 2. refer to table 23, ?command bus operations? on page 45 for valid a in or d in . 3. sampled, but not 100% tested. 4. see figure 11, ?ac input/output reference waveform? on page 34 for timing measurements and maximum allowable input slew rate. 5. see figure 10, ?write operations waveform? on page 33 . figure 10: write operations waveform w10 w1 w7 w4 w9 w9 w3 w3 w2 w6 w8 w5 a d d re ss [ a ] ce# [e] we# [w] oe# [g] data [d/q] rp# [p] vpp [v]
c3 discrete datasheet march 2008 34 290645-24 7.3 erase and program timings table 17: erase and program timings 7.4 ac i/o test conditions note: input timing begins, and output timing ends, at v ccq /2. input rise and fall times (10% to 90%) < 5 ns. worst-case speed conditions are when v cc = v cc min. symbol parameter v pp 1.65 v?3.6 v 11.4 v?12.6 v unit note typ max typ max t bwpb 4-kw parameter block word program time 1, 2, 3 0.10 0.30 0.03 0.12 s t bwmb 32-kw main block word program time 1, 2, 3 0.8 2.4 0.24 1 s t whqv1 / t ehqv1 word program time for 0.13 and 0.18 micron product 1, 2, 3 12 200 8 185 s word program time for 0.25 micron product 1, 2, 3 22 200 8 185 s t whqv2 / t ehqv2 4-kw parameter block erase time 1, 2, 30.540.44 s t whqv3 / t ehqv3 32-kw main block erase time 1, 2, 3 1 5 0.6 5 s t whrh1 / t ehrh1 program suspend latency 1,3 5 10 5 10 s t whrh2 / t ehrh2 erase suspend latency 1,3 5 20 5 20 s notes: 1. typical values measured at t a = +25 c and nominal voltages. 2. excludes external system-level overhead. 3. sampled, but not 100% tested. figure 11: ac input/output reference waveform v ccq 0v v ccq /2 v ccq /2 t e s t p o i n t s input outpu t
march 2008 datasheet 290645-24 35 c3 discrete note: see table 17 for component values. 7.5 device capacitance t a = 25 c, f = 1 mhz figure 12: transient equiva lent testing load circuit table 18: test configuration component va lues for worst-case speed conditions test configuration c l (pf) r 1 (k )r 2 (k ) v ccq min standard test 50 25 25 note: c l includes jig capacitance. device under test v ccq c l r 2 r 1 out table 19: device capacitance symbol parameter typ max unit condition c in input capacitance 6 8 pf v in = 0.0 v c out output capacitance 8 12 pf v out = 0.0 v sampled, not 100% tested.
c3 discrete datasheet march 2008 36 290645-24 8.0 power and reset specifications numonyx? flash devices have a tiered approach to power savings that can significantly reduce overall system power consumption. the automatic power savings (aps) feature reduces power consumption when the device is selected but idle. if ce# is deasserted, the flash enters its standby mode, where current consumption is even lower. if rp# is deasserted, the flash enter deep power-down mode for ultra-low current consumption. the combination of these features can minimize memory power consumption, and therefore, overall system power consumption. 8.1 active power (program/erase/read) with ce# at a logic - low level and rp# at a logic - high level, the device is in the active mode. refer to the dc characteristic tables for i cc current values. active power is the largest contributor to overall system power consumption. minimizing the active current could have a profound effect on system power consumption, especially for battery - operated devices. 8.2 automatic power savings (aps) automatic power savings provides low - power operation during read mode. after data is read from the memory array and the address lines are idle, aps circuitry places the device in a mode where typical current is comparable to i ccs . the flash stays in this static state with outputs valid until a new location is read. 8.3 standby power when ce# is at a logic - high level (v ih ), the flash memory is in standby mode, which disables much of the device?s circuitry and substantially reduces power consumption. outputs are placed in a high - impedance state independent of the status of the oe# signal. if ce# transitions to a logic - high level during erase or program operations, the device will continue to perform the operation and consume corresponding active power until the operation is completed. system engineers should analyze the breakd own of standby time versus active time and quantify the respective power consumption in each mode for their specific application. this approach will provide a more accurate measure of application - specific power and energy requirements. 8.4 deep power-down mode the deep power-down mode is activated when rp# = v il . during read modes, rp# going low de-selects the memory and places the outputs in a high-impedance state. recovery from deep power-down requires a minimum time of t phqv for read operations, and t phwl /t phel for write operations. during program or erase modes, rp# transitioning low aborts the in-progress operation. the memory contents of the address being programmed or the block being erased are no longer valid as the data integrity has been compromised by the abort. during deep power-down, all internal circuits are switched to a low-power savings mode (rp# transitioning to v il or turning off power to the device clears the status register).
march 2008 datasheet 290645-24 37 c3 discrete 8.5 power and reset considerations 8.5.1 power-up/down characteristics to prevent any condition that may result in a spurious write or erase operation, numonyx recommends to power-up vcc and vccq together. conversely, vcc and vccq must power-down together. numonyx also recommends that you power-up vpp with or after vcc has reached vcc min . conversely, vpp must powerdown with or slightly before vcc. if vccq and/or vpp are not connected to the vcc supply, then vcc must attain vcc min before applying vccq and vpp. device inputs must not be driven before supply voltage reaches vcc min . power supply transitions must only occur when rp# is low. 8.5.2 rp# connected to system reset the use of rp# during system reset is important with automated program/erase devices since the system reads from the flash memory when it comes out of reset. if a cpu reset occurs without a flash memory rese t, proper cpu initialization will not occur because the flash memory may be providing status information instead of array data. numonyx recommends connecting rp# to the system cpu reset# signal to allow proper cpu/flash initialization following system reset. system designers must guard against spurious writes when v cc voltages are above v lko . because both we# and ce# must be lo w for a command write, driving either signal to v ih will inhibit writes to the device. the cui architecture provides additional protection since alteration of memory contents can only occur after successful completion of the two-step command sequence s. the device is also disabled until rp# is brought to v ih , regardless of the state of its control inputs. by holding the device in reset during power-up/down, invalid bus co nditions during power-up can be masked, providing yet another level of memory protection. 8.5.3 v cc , v pp and rp# transitions the cui latches commands as issued by system software and is not altered by v pp or ce# transitions or wsm actions. its default state upon power-up, after exit from reset mode or after v cc transitions above v lko (lockout voltage), is read-array mode. after any program or block-erase operation is complete (even after v pp transitions down to v pplk ), the cui must be reset to read-arr ay mode by the read array command if access to the flash-memory array is desired. 8.5.4 reset specifications table 20: reset specifications symbol parameter v cc 2.7 v ? 3.6 v unit notes min max t plph rp# low to reset during read (if rp# is tied to v cc , this specification is not applicable) 100 ns 1, 2
c3 discrete datasheet march 2008 38 290645-24 8.6 power supply decoupling flash memory power-switching characterist ics require careful device decoupling. system designers should consider the following three supply current issues: ? standby current levels (i ccs ) ? read current levels (i ccr ) ? transient peaks produced by falling and rising edges of ce#. transient current magnitudes depend on the device outputs? capacitive and inductive loading. two-line control and proper decoup ling capacitor selection will suppress these transient voltage peaks. each flash device should have a 0.1 f ceramic capacitor connected between each v cc and gnd, and between its v pp and vss. these high- frequency, inherently low-inductance capacitors should be placed as close as possible to the package leads. t plrh1 rp# low to reset duri ng block erase 22 s 3 t plrh2 rp# low to reset during program 12 s 3 notes: 1. if t plph is < 100 ns the device may still reset but this is not guaranteed. 2. if rp# is asserted while a block erase or word program operat ion is not executing, the reset will complete within 100 ns. 3. sampled, but not 100% tested. figure 13: reset op erations waveforms table 20: reset specifications symbol parameter v cc 2.7 v ? 3.6 v unit notes min max ih v il v rp# (p) plph t ih v il v rp# (p) plph t (a ) r eset during r ead m ode abort complete phqv t phw l t phel t phqv t phw l t phel t (b) reset during program or block erase, < plph t plrh t plrh t ih v il v rp# (p) plph t abort complete phqv t phw l t phel t plrh t deep power- down (c ) r eset p rogram or b lock e rase, > plph t plrh t
march 2008 datasheet 290645-24 39 c3 discrete 9.0 device operations the c3 discrete device uses a cui and auto mated algorithms to simplify program and erase operations. the cui allows for 100% cmos - level control inputs and fixed power supplies during erasure and programming. the internal wsm completely automates program and erase operations while the cui signals the start of an operation and the status register reports device status. the cui handles the we# interface to the data and address latches as well as system status requests during wsm operation. 9.1 bus operations the c3 discrete device performs read, program, and erase operations in - system through the local cpu or microcontroller. fo ur control pins (ce#, oe#, we#, and rp#) manage the data flow in an d out of the flash device. table 21 on page 39 summarizes these bus operations. 9.1.1 read when performing a read cycle, ce# and oe # must be asserted; we# and rp# must be deasserted. ce# is the device selection control; when active low, it enables the flash memory device. oe# is the data output control; when low, data is output on dq[15:0]. see figure 9, ?read operation waveform? on page 29 . 9.1.2 write a write cycle occurs when both ce# and we# are low; rp# and oe# are high. commands are issued to the command user in terface (cui). the cui does not occupy an addressable memory location. address and data are latched on the rising edge of the we# or ce# pulse, whichever occurs first. see figure 10, ?write operations waveform? on page 33 . 9.1.3 output disable with oe# at a logic - high level (v ih ), the device outputs are disabled. dq[15:0] are placed in a high - impedance state. 9.1.4 standby deselecting the device by bringing ce# to a logic - high level (v ih ) places the device in standby mode, which substantially reduces device power consumption without any latency for subsequent read accesses. in standby, outputs are placed in a high- table 21: bus operations mode rp# ce# oe# we# dq[15:0] read v ih v il v il v ih d out write v ih v il v ih v il d in output disable v ih v il v ih v ih high-z standby v ih v ih xxhigh-z reset v il xxxhigh-z note: x = don?t care (v il or v ih )
c3 discrete datasheet march 2008 40 290645-24 impedance state independent of oe#. if deselected during a program or erase operation, the device continues to consum e active power until the program or erase operation is complete. 9.1.5 reset from read mode, rp# at v il for time t plph deselects the memory, places output drivers in a high - impedance state, and turns off all internal circuits. after return from reset, a time t phqv is required until the initial re ad-access outputs are valid. a delay (t phwl or t phel ) is required after return from reset before a write cycle can be initiated. after this wake - up interval, normal operation is restored. the cui resets to read-array mode, the status register is set to 0x80, and all blocks are locked. see figure 13, ?reset operations waveforms? on page 38 . if rp# is taken low for time t plph during a program or erase operation, the operation will be aborted; the memory contents at the aborted location (for a program) or block (for an erase) are no longer valid, since the data may be partially erased or written. the abort process goes through the following sequence: 1. when rp# goes low, the device shuts down the operation in progress, a process which takes time t plrh to complete. 2. after time t plrh , the part will either reset to read-array mode (if rp# is asserted during t plrh ) or enter reset mode (if rp# is deasserted after t plrh ). see figure 13, ?reset operations waveforms? on page 38 . in both cases, after returning from an aborted operation, the relevant time t phqv or t phwl /t phel must be observed before a read or wr ite operation is initiated, as discussed in the previous paragraph. however, in this case, these delays are referenced to the end of t plrh rather than when rp# goes high. as with any automated device, it is import ant to assert rp# during a system reset. when the system comes out of reset, th e processor reads from the flash memory. automated flash memories provide status information when read during program or block-erase operations. if a cpu reset occurs with no flash memory reset, proper cpu initialization may not occur because the flash memory may be providing status information instead of array data. numo nyx? flash memories allow proper cpu initialization following a system reset thro ugh the use of the rp# input. in this application, rp# is controlled by the same reset# signal that resets the system cpu.
march 2008 datasheet 290645-24 41 c3 discrete 10.0 modes of operation 10.1 read mode the flash memory has four read modes (read ar ray, read identifier, read status, and cfi query) and two write modes (program and erase). three additional modes (erase suspend to program, erase suspend to read, and program suspend to read) are available only during suspended operations. table 23, ?command bus operations? on page 45 and table 24, ?command codes and descriptions? on page 46 summarize the commands used for these modes. appendix a, ?write state machine states? on page 53 is a comprehensive chart showing the state transitions. 10.1.1 read array when rp# transitions from v il (reset) to v ih , the device defaults to read-array mode and will respond to the read-control inputs (ce#, address inputs, and oe#) without any additional cui commands. when the device is in read array mode, four control signals control data output. ? we# must be logic high (v ih ) ? ce# must be logic low (v il ) ? oe# must be logic low (v il ) ? rp# must be logic high (v ih ) in addition, the address of the desired locati on must be applied to the address pins. if the device is not in read-array mode, as would be the case after a program or erase operation, the read array command (0xff) must be issued to the cui before array reads can occur. 10.1.2 read identifier the read-identifier mode outp uts three types of information: the manufacturer/device identifier, the block locking status, and the prot ection register. the device is switched to this mode by issuing the read identifier command (0x90). once in this mode, read cycles from addresses shown in ta b l e 2 2 retrieve the specified information. to return to read-array mode, issue the read array command (0xff).
c3 discrete datasheet march 2008 42 290645-24 10.1.3 cfi query the cfi query mode outputs common flash interface (cfi) data after issuing the read query command (0x98). the cfi data structure contains information such as block size, density, command set, and electrical spec ifications. once in this mode, read cycles from addresses shown in appendix c, ?common flash interface,? retrieve the specified information. to return to read-array mo de, issue the read array command (0xff). 10.1.4 read status register the status register indicates the status of device operations and the success/failure of that operation. the read status register (0x70) command causes subsequent reads to output data from the status register until another command is issued. to return to reading from the array, issue a read array (0xff) command. the status register bits are output on dq[7:0]. the upper byte, dq[15:8], outputs 0x00 when a read status register command is issued. the contents of the status register are latched on the falling edge of oe# or ce# (whichever occurs last) which prevents possible bus errors that might occur if status register contents change while being read . ce# or oe# must be toggled with each subsequent status read, or the status register will not indicate completion of a program or erase operation. table 22: device identification codes item address 1 data description base offset manufacturer id block 0x00 0x0089 device id block 0x01 0x88c0 8-mbit top boot device 0x88c1 8-mbit bottom boot device 0x88c2 16-mbit top boot device 0x88c3 16-mbit bottom boot device 0x88c4 32-mbit top boot device 0x88c5 32-mbit bottom boot device 0x88cc 64-mbit top boot device 0x88cd 64-mbit bottom boot device block lock status 2 block 0x02 dq0 = 0b0 block is unlocked dq0 = 0b1 block is locked block lock-down status 2 block 0x02 dq1 = 0b0 block is not locked-down dq1 = 0b1 block is locked down protection register lock status block 0x80 lock data protection register block 0x81 - 0x88 register data multiple reads requ ired to read the entire 128-bit protection register. notes: 1. the address is constructed from a base address plus an o ffset. for example, to read the block lock status for block number 38 in a bottom boot device, se t the address to 0x0f8000 plus the offset (0x02), i.e. 0x0f8002. then examine dq0 of the data to determin e if the block is locked. 2. see section 11.2, ?reading block-lock status? on page 49 for valid lock status.
march 2008 datasheet 290645-24 43 c3 discrete when the wsm is active, sr[7] will indicate the status of the wsm; the remaining bits in the status register indicate whether the wsm was successful in performing the preferred operation see table 25, ?status register bit definition? on page 47 . 10.1.4.1 clear status register the wsm can set status register bits 1 thro ugh 7 and can clear bits 2, 6, and 7, but the wsm cannot clear status register bits 1, 3, 4 or 5. because bits 1, 3, 4, and 5 indicate various error conditions, these bits can be cleared only through the clear status register (0x50) command. by allowing the system software to control the resetting of these bits, several operations may be performed (s uch as cumulatively programming several addresses or erasing multiple blocks in sequence) before reading the status register to determine if an error occurred during that series. clear the status register before beginning anothe r command or sequence. the read array command must be issued before data can be read from the memory array. resetting the device also clears the status register. 10.2 program mode programming is executed using a two - write cycle sequence. the program setup command (0x40) is issued to the cui, follo wed by a second write that specifies the address and data to be programmed. the ws m will execute a sequence of internally timed events to program preferred bits of th e addressed location, then verify the bits are sufficiently programmed. programming the me mory results in specific bits within an address location being changed to a ?0.? if users attempt to program ?1?s, the memory cell contents do not change and no error occurs. the status register indicates programming status. while the program sequence executes, status bit 7 is ?0.? the status register can be polled by toggling either ce# or oe#. while programming, the only valid commands are read status register, program suspend, and program resume. when programming is complete, the program-status bits must be checked. if the programming operation was unsuccessful, sr[4] is set to indicate a program failure. if sr[3] is set, then v pp was not within acceptable limits, and the wsm did not execute the program command. if sr[1] is set, a program operation was attempted on a locked block and the operation was aborted. the status register should be cleared before attempting the next operation. any cui instruction can follow after programming is co mpleted; however, to prevent inadvertent status register reads, be sure to reset the cui to read-array mode. 10.2.1 12-volt production programming when v pp is between 1.65 v and 3.6 v, all program and erase current is drawn through the vcc pin. note: if v pp is driven by a logic signal, v ih min = 1.65 v. that is, v pp must remain above 1.65 v to perform in-system flash modifications. when v pp is connected to a 12 v power supply, the device draws program and erase current directly from the vpp pin. this elim inates the need for an external switching transistor to control v pp . figure 16 on page 52 shows examples of how the flash power supplies can be configured for various usage models. the 12 v v pp mode enhances programming performance during the short period of time typically found in manufacturing proc esses; however, it is not intended for extended use. you cna apply 12 v to vpp during program and erase operations for a
c3 discrete datasheet march 2008 44 290645-24 maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks. vpp may be connected to 12 v for a total of 80 hours maximum. stressing the device beyond these limits may cause permanent damage. 10.2.2 suspending and resuming program the program suspend command halts an in - progress program operation so that data can be read from other locations of memory. once the programming process starts, issuing the program suspend command to th e cui requests that the wsm suspend the program sequence at predetermined points in the program algorithm. the device continues to output status register data after the program suspend command is issued. polling sr[7] and sr[2] will determin e when the program operation has been suspended (both will be set to ?1?). the program-suspend latency is specified with t whrh1 /t ehrh1 . a read-array command can now be issued to the cui to read data from blocks other than that which is suspended. the only other valid commands while program is suspended are read status register, read identifier, cfi query, and program resume. after the program resume command is i ssued to the flash memory, the wsm will continue with the programming process and sr[2] and sr[7] will automatically be cleared. the device automatically outputs status register data when read (see figure 18, ?program suspend / resume flowchart? on page 57 ) after the program resume command is issued. v pp must remain at the same v pp level used for program while in program-suspend mode. rp# must also remain at v ih . 10.3 erase mode to erase a block, issue the erase set - up and erase confirm commands to the cui, along with an address identifying the block to be erased. this address is latched internally when the erase confirm command is issued. block erasure results in all bits within the block being set to ?1.? only one block can be erased at a time. the wsm will execute a sequence of internally timed events to program all bits within the block to ?0,? erase all bits within the block to ?1,? then verify that all bits within the block are sufficiently erased. while the erase executes, status bit 7 is a ?0.? when the status register indicates that eras ure is complete, check the erase-status bit to verify that the erase operation was successful. if the erase operation was unsuccessful, sr[5] of the status register will be set to a ?1,? indicating an erase failure. if v pp is not within acceptable limits after the erase confirm command was issued, the wsm will not execute the erase sequence; instead, sr[5] of the status register is set to indicate an erase error, and sr[3] is set to a ?1? to identify that v pp supply voltage is not within acceptable limits. after an erase operation, clear the status register (0x50) before attempting the next operation. any cui instruction can follow after erasure is completed; however, to prevent inadvertent status- register reads, numonyx recommends that you place the flash in read-array mode af ter the erase is complete. 10.3.1 suspending and resuming erase since an erase operation requires on the order of seconds to complete, an erase suspend command is provided to allow erase - sequence interruption to read data from?or program data to? another block in memory. once the erase sequence is started, issuing the erase suspend command to the cui suspends the erase sequence at a predetermined point in the erase algori thm. the status register indicates if/when the erase operation has been suspended. erase-suspend latency is specified by t whrh2 / t ehrh2 .
march 2008 datasheet 290645-24 45 c3 discrete a read array or program command can now be issued to the cui to read/program data from/to blocks other than that which is suspended. this nested program command can subsequently be suspended to read yet another location. the only valid commands while erase is suspended are read status register, read identifier, cfi query, program setup, program resume, erase resume, lock block, unlock block, and lock-down block. during erase-suspend mode, th e device can be placed in a pseudo - standby mode by taking ce# to v ih , which reduces active current consumption. erase resume continues the erase sequence when ce# = v il . similar to the end of a standard erase operation, the status register must be read and cleared before the next instruction is issued. bus operations are defined in table 21, ?bus operations? on page 39 . table 23: command bus operations command notes first bus cycle second bus cycle oper addr data oper addr data read array 1,3 write x 0xff read identifier 1,3 write x 0x90 read ia id cfi query 1,3 write x 0x98 read qa qd read status register 1,3 write x 0x70 read x srd clear status register 1,3 write x 0x50 program 2,3 write x 0x40/0x10 write pa pd block erase/confirm 1,3 write x 0x20 write ba d0h program/erase suspend 1,3 write x 0xb0 program/erase resume 1,3 write x 0xd0 lock block 1,3 write x 0x60 write ba 0x01 unlock block 1,3 write x 0x60 write ba 0xd0 lock-down block 1,3 write x 0x60 write ba 0x2f protection program 1,3 write x 0xc0 write pa pd x = "don?t care" pa = prog addr ba = block addr ia = identifier addr. qa = query addr. srd = status reg. data pd = prog data id = identifier data qd = query data notes: 1. following the read identifier or cfi query commands, read operations output device identification data or cfi query information, respectively. see section 10.1.2 and section 10.1.3 . 2. either 0x40 or 0x10 command is valid, but the numonyx standard is 0x40. 3. when writing commands, the upper data bus [dq8-dq15] should be either v il or v ih , to minimize current draw.
c3 discrete datasheet march 2008 46 290645-24 table 24: command codes and descriptions code (hex) device mode command description ff read array this command places the device in read-array mode, which outputs array data on the data pins. 40 program set-up this is a two - cycle command. the first cycle prepares the cui for a program operation. the second cycle latches addresses and data information and initiates the wsm to execute the program algorithm. the flash outputs status register da ta when ce# or oe# is toggled. a read array command is required after progra mming to read array data. see section 10.2, ?program mode? on page 43 . 20 erase set-up this is a two - cycle command. it prepares the cui for the erase confirm co mmand. if the next command is not an erase confirm command, then the cui will (a) set both sr.4 and sr.5 to ?1,? (b) place the device into the read-status regist er mode, and (c) wait for another command. see section 10.3, ?erase mode? on page 44 . d0 erase confirm program/erase resume unlock block if the previous command was an erase set-up command, then the cui w ill close the address and data latches and begin erasing the block indicated on the address pins. during program/erase, the device will respond only to the read status register, program suspend and erase suspend commands, and will output status regist er data when ce# or oe# is toggled. if a program or erase operation was previously suspended, this command will resume that operation. if the previous command was block unlock set-up , the cui will latch the address and unlock the block indicated on the address pins. if the bloc k had been previously set to lock-down, this operation will have no effect. (see section 11.1 ) b0 program suspend erase suspend issuing this command will begin to suspend the currently executin g program/erase operation. the status register will indicate when the operation has been successfully suspended by setting either the program-suspend sr[2] or erase-suspend sr[6] and the wsm status bit sr[7] to a ?1? (ready). the wsm will continue to idle in the suspend state, regard less of the state of all input- control pins except rp#, which will immediately s hut down the wsm and the remainder of the chip if rp# is driven to v il . see sections 3. 2.5.1 and 3.2.6.1. 70 read status register this command places the device into read-status register mode. reading the device will output the contents of the status register, regardless of the address presented to the device. the device automatically enters this mode after a progra m or erase operation has been initiated. see section 10.1.4, ?read status register? on page 42 . 50 clear status register the wsm can set the block-lock status sr[1], v pp status sr[3], program status sr[4], and erase- status sr[5] bits in the status register to ?1,? but it cannot clear them to ?0.? issuing this command clears those bits to ?0.? 90 read identifier this command puts the device into the read-identifier mode so th at reading the device will output the manufacturer/device codes or block-lock status. see section 10.1.2, ?read identifier? on page 41 . 60 block lock, block unlock, block lock-down set-up this command prepares the cui for block-locking changes. if the next command is not block unlock, block lock, or block lock-down, then the cui will set both the program and erase-status register bits to indicate a command-sequence error. see section 11.0, ?security modes? on page 48 . 01 lock-block if the previous command was lo ck set-up, the cui will latch th e address and lock the block indicated on the address pins. (see section 11.1 ) 2f lock-down if the previous command was a lock-down set-up command, the cui will latch the address and lock-down the block indicated on the address pins. (see section 11.1 ) 98 cfi query this command puts the device in to the cfi-query mode so that reading the device will output common flash interface information. see section 10.1.3 and appendix c, ?common flash interface? . c0 protection program set-up this is a two-cycle command. the first cycle pr epares the cui for a program operation to the protection register. the second cycle latches addr esses and data informati on and initiates the wsm to execute the protection program algorithm to the protection register. the flash outputs status register data when ce# or oe# is toggled. a read array command is required after programming to read array data. see section 11.5 . 10 alt. prog set-up operates the same as program set - up command. (see 0x40/program set-up) 00 invalid/ reserved unassigned commands should not be used. numonyx reserves the right to redefine these codes for future functions. note: see appendix a, ?write state machine states? for mode transition information.
march 2008 datasheet 290645-24 47 c3 discrete table 25: status register bit definition wsms ess es ps vpps pss bls r 76543210 notes: sr[7] write state machine status (wsms) 1=ready 0=busy before checking program or erase- status bits, check the write state machine bit first to determine word program or block erase completion. sr[6] = erase - suspend status (ess) 1 = erase suspended 0 = erase in progress/completed when erase suspend is issued, wsm halts execution and sets both wsms and ess bits to ?1.? ess bit remains set to ?1? until an erase resume command is issued. sr[5] = erase status (es) 1=error in block erase 0 = successful block erase when this bit is set to ?1,? wsm has applied the maximum number of erase pulses to the bloc k and is still unable to verify successful block erasure. sr[4] = program status (ps) 1 = error in programming 0 = successful programming when this bit is set to ?1,? wsm has attempted but failed to program a word/byte. sr[3] = v pp status (vpps) 1=v pp low detect, operation abort 0=v pp ok the v pp status bit does not provide continuous indication of v pp level. the wsm interrogates v pp level only after the program or erase command sequences have been entered and informs the system if v pp has not been switched on. the v pp is also checked before the operation is verified by the wsm. the v pp status bit is not guaranteed to report accurate feedback between v pplk and v pp1 min. sr[2] = program suspend status (pss) 1=program suspended 0 = program in progress/completed when program suspend is issued, wsm halts execution and sets both wsms and pss bits to ?1.? pss bit remains set to ?1? until a program resume command is issued. sr[1] = block lock status 1 = prog/erase attempted on a locked block; operation aborted. 0 = no operation to locked blocks if a program or erase operation is attempted to one of the locked blocks, this bit is set by the wsm. the operation specified is aborted an d the device is returned to read status mode. sr[0] = reserved for future enhancements (r) this bit is reserved for future use and should be masked out when polling the status register. note: a command-sequence error is indicated when sr[4], sr[5], and sr[7] are set.
c3 discrete datasheet march 2008 48 290645-24 11.0 security modes 11.1 flexible block locking the c3 discrete device offers an instant, individual block-locking scheme that allows any block to be locked or unlocked with no latency, enabling instant code and data protection. this locking scheme offers two levels of prot ection. the first level allows software-only control of block locking (useful for data bl ocks that change frequently), while the second level requires hardware interaction before locking can be changed (useful for code blocks that change infrequently). the following sections will discuss the operatio n of the locking system. the term ?state [abc]? will be used to spec ify locking states; for example, ?state [001],? where a = value of wp#, b = bit d1 of the block lo ck status register, and c = bit d0 of the block lock status register. figure 14, ?block locking state diagram? on page 48 displays all of the possible locking states. 11.1.1 locking operation the locking status of each block can be set to locked, unlocked, or lock-down, each of which will be described in the following sections. see figure 14, ?block locking state diagram? on page 48 and figure 21, ?locking operations flowchart? on page 60 . figure 14: block locking state diagram [x00] [x01] power-up/reset unlocked locked [011] [111] [110] locked- down 4, 5 software locked [011] hardware locked 5 unlocked wp# hardware control notes: 1. [a,b,c] represents [wp#, d1, d0]. x = don?t care. 2. d1 indicates block lock-down status. d1 = ?0?, lock-down has not been issued to this block. d1 = ?1?, lock-down has been issued to this block. 3. d0 indicates block lock status. d0 = ?0?, block is unlocked. d0 = ?1?, block is locked. 4. locked-down = hardware + software locked. 5. [011] states should be tracked by system software to determine difference between hardware locked and locked-down states. s oftware b l ock lock (0x60/0x01) or s oftware b l ock unl ock (0x60/0xd0) s oftware b l ock lock-down (0x60/0x2f) wp# hardware control
march 2008 datasheet 290645-24 49 c3 discrete the following paragraph concisely su mmarizes the locking functionality. 11.1.1.1 locked state the default state of all blocks upon power-up or reset is locked (states [001] or [101]). locked blocks are fully protected from al teration. any program or erase operations attempted on a locked block will return an error on bit sr[1]. the state of a locked block can be changed to unlocked or lock down using the appropriate software commands. an unlocked block can be locked by writing the lock command sequence, 0x60 followed by 0x01. 11.1.1.2 unlocked state unlocked blocks (states [000], [100], [110]) can be programmed or erased. all unlocked blocks return to the locked state when the device is reset or powered down. the status of an unlocked block can be changed to locked or locked down using the appropriate software commands. a locked bl ock can be unlocked by writing the unlock command sequence, 0x60 followed by 0xd0. 11.1.1.3 lock-down state blocks that are locked-down (state [011]) are protected from program and erase operations (just like locked blocks), but their protection status cannot be changed using software commands alone. a locked or unlocked block can be locked down by writing the lock-down command sequence , 0x60 followed by 0x2f. locked-down blocks revert to the locked state when the device is reset or powered down. the lock-down function depends on the wp# input pin. when wp# = 0, blocks in lock down [011] are protected from program, erase, and lock status changes. when wp# = 1, the lock-down function is disabled ([111]), and locked-down blocks can be individually unlocked by software command to the [110] state, where they can be erased and programmed. these blocks can then be relocked [111] and unlocked [110] as required while wp# remains high. when wp # goes low, blocks that were previously locked down return to the lock-down stat e [011], regardless of any changes made while wp# was high. device reset or power-down resets all blocks, including those in lock-down, to locked state. 11.2 reading block-lock status the lock status of each block can be read in read-identifier mode of the device by issuing the read-identifier command (0x90). subsequent reads at block address + 0x00002 will output the lock status of that block. the lock status is represented by dq0 and dq1: ? dq0 indicates the block lock/unlock status and is set by the lock command and cleared by the unlock command. it is also automatically set when entering lock down. ? dq1 indicates lock-down status and is set by the lock-down command. it cannot be cleared by software?only by device reset or power-down. see table 22, ?device identification codes? on page 42 for block-status information. 11.3 locking operations during erase suspend changes to block-lock status can be perfor med during an erase-suspend by using the standard locking command sequences to unlo ck, lock, or lock down a block. this operation is useful in the case when anothe r block needs to be updated while an erase operation is in progress.
c3 discrete datasheet march 2008 50 290645-24 to change block locking during an erase operation, first issue the erase suspend command (0xb0), and then check the status register until it indicates that the erase operation has been suspended. next, write the preferred lock command sequence to a block and the lock status will be changed. after completing any preferred lock, read, or program operations, resume the erase operation with the erase resume command (0xd0). if a block is locked or locked down during a suspended erase of the same block, the locking status bits will be changed immediat ely. but when the erase is resumed, the erase operation will complete. locking operations cannot be performe d during a program suspend. refer to appendix a, ?write state machine states? on page 53 for detailed information on which commands are valid during erase suspend. 11.4 status register error checking using nested-locking or program-command sequences during erase suspend can introduce ambiguity into status register results. since locking changes are performed us ing a two-cycle command sequence, for example, 0x60 followed by 0x01 to lock a block. following the block lock, block unlock, or block lock-down setup command (0x60) with an invalid command will produce a lock-command error (sr[4] and sr[5] will be set to 1) in the status register. if a lock-command error occurs during an erase suspend, sr[4] and sr[5] will be set to 1 and will remain at 1 after the erase is resumed. when erase is complete, any possible error during the erase cannot be detected by the status register because of the previous lock-command error. a similar situation happens if an error occurs during a program-operation error nested within an erase suspend. 11.5 128-bit protection register the c3 device architecture includes a 128-bit protection register than can be used to increase the security of a system design. for example, the number contained in the protection register can be used to ?match? the flash component with other system components, such as the cpu or asic, preven ting device substitution. application note, ap-657 designing with the advanced+ boot block flash memory architecture, contains additional application information. the 128 bits of the protection register are divided into two 64-bit segments. one of the segments is programmed at the numonyx factory with a unique 64-bit number, which is unchangeable. the other segment is left blank for customer designs to program, as preferred. once the customer segment is programmed, it can be locked to prevent further programming. 11.5.1 reading the protection register the protection register is read in the read -identifier mode. the de vice is switched to this mode by issuing the read identifier command (0x90). once in this mode, read cycles from addresses shown in figure 15, ?protection register mapping ? retrieve the specified information. to return to read -array mode, issue the read array command (0xff).
march 2008 datasheet 290645-24 51 c3 discrete 11.5.2 programming the protection register the protection register bits are programme d using the two-cycle protection program command. the 64-bit number is programmed 16 bits at a time. first, issue the protection program setup command, 0xc0. th e next write to the device will latch in address and data and program the specified location. the allowable addresses are listed in table 22, ?device identification codes? on page 42 . see figure 22, ?protection register programming flowchart? on page 61 . attempting to program to a previously locked protection register segment will result in a status register error (program error bit sr[4] and lock error bit sr[1] will be set to 1). note: do not attempt to address protection program commands outside the defined protection register address space; status register can be indeterminate. 11.5.3 locking the protection register the user-programmable segment of the protecti on register is lockable by programming bit 1 of the pr-lock location to 0. bit 0 of this location is programmed to 0 at the numonyx factory to protect the unique devi ce number. this bit is set using the protection program command to program 0xfffd to the pr-lock location. after these bits have been programmed, no further changes can be made to the values stored in the protection register. protection program commands to a locked section will result in a status register error (program error bit sr[4] and lock error bit sr[1] will be set to 1). protection register lockout state is not reversible. 11.6 v pp program and erase voltages the c3 device provides in-system programming and erase in the 1.65 v?3.6 v range. for fast production programming, 12 v programming can be used. 11.6.1 program protection in addition to the flexib le block locking, the v pp programming voltage can be held low for absolute hardware write protection of all blocks in the flash device. when v pp is below or equal to v pplk , any program or erase operation will result in an error, prompting the corresponding status register bit (sr[3]) to be set. figure 15: protection register mapping 0x88 0x85 64-bit segment (user-programmable) 0x84 0x81 0x80 pr lock register 0 64-bit segment (intel factory-programmed) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 128-bit protection register 0
c3 discrete datasheet march 2008 52 290645-24 note: 1. a resistor can be used if the v cc supply can sink adequate current based on resistor value. see ap-657 designing with the advanced+ boot block flash memory architecture for details. figure 16: example power supply configurations v cc v pp 12 v fast programming absolute write protection with v pp v pplk system supply 12 v supply 10 k v cc v pp system supply 12 v supply low voltage and 12 v fast programming v cc v pp system supply prot# (logic signal) v cc v pp system supply low-voltage programming low-voltage programming absolute write protection via logic signal (note 1)
march 2008 datasheet 290645-24 53 c3 discrete appendix a write state machine states ta b l e 2 6 and ta b l e 2 7 show the write state machine command state transitions based on incoming commands. table 26: write state machine states (sheet 1 of 2) command input (and next state) current state sr. 7 data when read read array (ffh) program setup (10/ 40h) erase setup (20h) erase confirm (d0h) prog/ers suspend (b0h) prog/ ers resume (d0) read status (70h) clear status (50h) read array ?1? array read array prog. setup ers. setup read array read sts. read array read status ?1? status read array prog. setup ers. setup read array read sts. read array read config. ?1? config read array prog. setup ers. setup read array read sts. read array read query ?1? cfi read array prog. setup ers. setup read array read sts. read array lock setup ?1? status lock command error lock (done) lock cmd. error lock (done) lock cmd. error lock cmd. error ?1? status read array prog. setup ers. setup read array read sts. read array lock oper. (done) ?1? status read array prog. setup ers. setup read array read sts. read array prot. prog. setup ?1? status protection register program prot. prog. (not done) ?0? status protection register program (not done) prot. prog. (done) ?1? status read array prog. setup ers. setup read array read sts. read array prog. setup ?1? status program program (not done) ?0? status program (not done) prog. sus. status program (not done) prog. susp. status ?1? status prog. sus. read array program suspend read array prog. (not done) prog. sus. rd. array program (not done) prog. sus. status prog. sus. rd. array prog. susp. read array ?1? array prog. sus. read array program suspend read array prog. (not done) prog. sus. rd. array program (not done) prog. sus. status prog. sus. rd. array prog. susp. read config ?1? config prog. sus. read array program suspend read array prog. (not done) prog. sus. rd. array program (not done) prog. sus. status prog. sus. rd. array prog. susp. read query ?1? cfi prog. sus. read array program suspend read array prog. (not done) prog. sus. rd. array program (not done) prog. sus. status prog. sus. rd. array program (done) ?1? status read array prog. setup ers. setup read array read status read array erase setup ?1? status erase command error erase (not done) erase cmd. error erase (not done) erase command error
c3 discrete datasheet march 2008 54 290645-24 erase cmd. error ?1? status read array prog. setup ers. setup read array read status read array erase (not done) ?0? status erase (not done) erase sus. status erase (not done) ers. susp. status ?1? status erase sus. read array prog. setup ers. sus. rd. array erase ers. sus. rd. array erase erase sus. status ers. sus. rd. array erase susp. array ?1? array erase sus. read array prog. setup ers. sus. rd. array erase ers. sus. rd. array erase erase sus. status ers. sus. rd. array ers. susp. read config ?1? config erase sus. read array prog. setup ers. sus. rd. array erase ers. sus. rd. array erase erase sus. status ers. sus. rd. array ers. susp. read query ?1? cfi erase sus. read array prog. setup ers. sus. rd. array erase ers. sus. rd. array erase erase sus. status ers. sus. rd. array erase (done) ?1? status read array prog. setup ers. setup read array read sts. read array table 27: write state machine states, continued command input (and next state) current state read config (90h) read query (98h) lock setup (60h) prot. prog. setup (c0h) lock confirm (01h) lock down confirm (2fh) unlock confirm (d0h) read array read config. read query lock setup prot. prog. setup read array read status read config. read query lock setup prot. prog. setup read array read config. read config. read query lock setup prot. prog. setup read array read query read config. read query lock setup prot. prog. setup read array lock setup locking command error lock operation (done) lock cmd. error read config. read query lock setup prot. prog. setup read array lock oper. (done) read config. read query lock setup prot. prog. setup read array prot. prog. setup protection register program prot. prog. (not done) protection register program (not done) prot. prog. (done) read config. read query lock setup prot. prog. setup read array prog. setup program program (not done) program (not done) prog. susp. status prog. susp. read config. prog. susp. read query program suspend read array program (not done) table 26: write state machin e states (sheet 2 of 2)
march 2008 datasheet 290645-24 55 c3 discrete prog. susp. read array prog. susp. read config. prog. susp. read query program suspend read array program (not done) prog. susp. read config. prog. susp. read config. prog. susp. read query program suspend read array program (not done) prog. susp. read query. prog. susp. read config. prog. susp. read query program suspend read array program (not done) program (done) read config. read query lock setup prot. prog. setup read array erase setup erase command error erase (not done) erase cmd. error read config. read query lock setup prot. prog. setup read array erase (not done) erase (not done) erase susp. status ers. susp. read config. erase suspend read query lock setup erase suspend read array erase (not done) erase suspend array ers. susp. read config. erase suspend read query lock setup erase suspend read array erase (not done) eras sus. read config erase suspend read config. erase suspend read query lock setup erase suspend read array erase (not done) eras sus. read query erase suspend read config. erase suspend read query lock setup erase suspend read array erase (not done) ers.(done) read config. read query lock setup prot. prog. setup read array table 27: write state machine states, continued
c3 discrete datasheet march 2008 56 290645-24 appendix b flow charts figure 17: word program flowchart program suspend loop start write 0x40, word address wr i te d ata, word address read status register sr[7] = full status check ( if desir ed) pr ogram complete suspend? 1 0 no yes word program procedure repeat for subsequent word program oper ations. full status register check can be done after each program , or after a sequence of progr am oper ations. write 0xff after the last oper ation to set to the read arr ay state. comments bus operation command data = 0x40 addr = location to progr am wr ite pr ogram setup data = data to pr ogr am addr = location to progr am wr ite data status register data: toggle ce# or oe# to update status register read none check sr[7] 1 = wsm ready 0 = wsm busy idle none (setup) (confi rm) full status check procedure read status register pr ogram successful sr[3] = sr[1] = 0 0 sr[4] = 0 1 1 1 v pp range error device protect err or progr am error sr[3] must be clear ed befor e the wr ite state machine will allow further progr am attem pts. if an err or is detected, clear the status register before continuing operations - only the clear staus register comm and clears the status register er ror bits. idle idle bus operation none none command check sr[3]: 1 = v pp error check sr[4]: 1 = data pr ogr am er ror comments idle none check sr[1]: 1 = block locked; oper ation aborted
march 2008 datasheet 290645-24 57 c3 discrete figure 18: program suspend / resume flowchart read status register sr[7] = sr[2] = read array data program completed done reading pr ogram resumed read arr ay data 0 no 0 yes 1 1 program suspend / resume procedure wr ite pr ogram resume data = 0xd0 addr = any address bus operation command comments wr ite pr ogram suspend data = 0xb0 addr = any address idle none check sr[7]: 1 = wsm r eady 0 = wsm busy idle none check sr[2]: 1 = program suspended 0 = program completed wr ite read array data = 0xff addr = any address read none read arr ay data from block other than the one being pr ogr ammed read none status r egister data toggle ce# or oe# to update status register addr = any address write 0xff (read a rray) write 0xd0 any address (p rogram resume) wr ite 0xff (read array) wr ite read status data = 0x70 addr = any address start write 0xb0 any address (program suspend) write 0x70 any address (read status)
c3 discrete datasheet march 2008 58 290645-24 figure 19: erase suspend / resume flowchart erase completed read array data 0 0 1 1 start read status register sr[7] = sr[6] = erase resumed done reading wr ite wr ite idle idle wr ite erase suspend read ar r ay or pr ogr am none none pr ogr am resume data = 0xb0 addr = any address data = 0xff or 0x40 addr = any address check sr[7]: 1 = wsm r eady 0 = wsm busy check sr[6]: 1 = erase suspended 0 = er ase completed data = 0xd0 addr = any address bus operation command comments read none status register data. toggle ce# or oe# to update status r egister ; addr = any address read or wr ite none read ar r ay or pr ogr am data fr om/to block other than the one being er ased erase suspend / resume procedure wr ite 0x70, any address (read status) wr ite 0xb0, any address (e rase s uspend) wr ite 0xd0, any address (erase resume) wr ite 0xff (read array) wr ite read status data = 0x70 addr = any address read ar r ay data wr i te 0xff 0 (read array) 1
march 2008 datasheet 290645-24 59 c3 discrete figure 20: block erase flowchart start full erase status check procedure repeat for subsequent block er asures. full status r egister check can be done after each block erase or after a sequence of block erasur es. wr ite 0xff after the last oper ation to enter r ead ar ray m ode. sr[1,3] must be clear ed befor e the wr ite state m achine will allow fur ther er ase attempts. only the clear status register com mand clear s sr[1, 3, 4, 5]. if an er ror is detected, clear the status r egister before attem pting an erase r etry or other err or r ecovery. no suspend erase 1 0 0 0 1 1,1 1 1 0 yes suspend erase loop 0 write 0x20, block address write 0xd0, block address read status register sr[7] = full erase status check (if desir ed) block erase complete read status register block erase successful sr[1] = block locked error block erase procedure bus operation command comments wr ite block erase setup data = 0x20 addr = block to be erased (ba) wr ite erase confirm data = 0xd0 addr = block to be erased (ba) read none status register data. toggle ce# or oe# to update status r egister data idle none check sr[7]: 1 = wsm ready 0 = wsm busy bus operation command comments sr[3] = v pp range error sr[4,5] = com mand sequence err or sr[5] = block erase error idle none check sr[3]: 1 = v pp range err or idle none check sr[4,5]: both 1 = com mand sequence err or idle none check sr[5]: 1 = block er ase err or idle none check sr[1]: 1 = attempted er ase of locked block; er ase aborted. (block erase) (erase confi rm)
c3 discrete datasheet march 2008 60 290645-24 figure 21: locking op erations flowchart no start write 0x60, block addr ess wr ite 0x90 read block lock status locking change? lock change complete wr ite either 0x01/0xd0/0x2f, block addr ess write 0xff any address yes wr ite wr ite wr ite (optional) read (optional) idle (optional) wr ite lock setup lock, unlock, or lock-down confirm read device id block lock status none read array data = 0x60 addr = any addr ess data = 0x01 ( block lock) 0xd0 (block unlock) 0x2f ( lock-down block) addr = block to lock/unlock/lock-down data = 0x90 addr = any addr ess block lock status data addr = block address + offset 2 confirm locking change on d[1,0] . data = 0xff addr = any addr ess bus operat ion command comments locking operations procedure (lock confi rm) (read device id) (read array) o ptional (lock s etup)
march 2008 datasheet 290645-24 61 c3 discrete figure 22: protection register programming flowchart full status check procedure program protection register oper ation addresses must be within the protection register addr ess space. addresses outside this space will return an error. repeat for subsequent programming operations. full status register check can be done after each pr ogram, or after a sequence of program operations. write 0xff after the last oper ation to set read ar ray state. sr[3] must be cleared before the write state machine will allow further progr am attempts. only the clear staus register comm and clears sr[1, 3, 4]. if an er ror is detected, clear the status r egister before attempting a pr ogram retry or other err or recovery. 1 0 1 1 protection register programming procedure start wr ite 0xc 0, pr address wr ite pr address & data read status register sr[7] = full status check ( if desired) program complete read status register data program successful sr[3], sr[4] = v pp range er ror program error register locked; program aborted idle idle bus operation none none command check sr[1], sr[3], sr[4]: 0,1,1 = v pp range err or check sr[1], sr[3], sr[4]: 0,0,1 = pr ogr amm ing err or comments write write idle program pr setup protection program none data = 0xc0 addr = fir st location to program data = data to program addr = location to program check sr[7]: 1 = wsm ready 0 = wsm busy bus operation command comments read none status register data. toggle ce# or oe# to update status register data idle none check sr[1], sr[3], sr[4]: 1,0,1 = block locked; oper ation aborted (program setup) (confirm data) 0 0 sr[3], sr[4] = 0 sr[3], sr[4] = 1
c3 discrete datasheet march 2008 62 290645-24 appendix c common flash interface this appendix defines the data structure or ?database? returned by the common flash interface (cfi) query command. system software should parse this structure to gain critical information such as block size, dens ity, x8/x16, and electrical specifications. once this information has been obtained, the software detects which command sets to use to enable flash writes, block erases, and otherwise control the flash component. the query is part of an overall specific ation for multiple command set and control interface descriptions called common flash interface, or cfi. c.1 query structure output the query database allows system software to obtain information for controlling the flash device. this section describes the device?s cfi-compliant interface that allows access to query data. query data are presented on the lowest-order data outputs (dq0-dq7) only. the numerical offset value is the address relative to the maximum bus width supported by the device. on this family of devices, the qu ery table device starting address is a 0x10, which is a word address for x16 devices. for a word-wide (x16) device, the first two query-structure bytes, ascii ?q? and ?r,? appear on the low byte at word addresses 0x10 and 0x11. this cfi-compliant device outputs 0x00 data on upper bytes. the devi ce outputs ascii ?q? in the low byte (dq0- dq7) and 0x00 in the high byte (dq8-dq15). at query addresses containing two or more bytes of information, the least-significant data byte is presented at the lower addre ss, and the most-significant data byte is presented at the higher address. for tables in this appendix, addresses and data are represented in hexadecimal notation, so the ?h? suffix has been dropped. in addition, since the upper byte of word- wide devices is always ?0x00,? the leading ?00? has been dropped from the table notation and only the lower byte value is shown. any x16 device outputs can be assumed to have 0x00 on the upper byte in this mode. table 28: summary of query structure outp ut as a function of device and mode device hex offset hex code ascii value device addresses 00010: 51 "q" 00011: 52 "r" 00012: 59 "y"
march 2008 datasheet 290645-24 63 c3 discrete c.2 query structure overview the query command causes the flash component to display the common flash interface (cfi) query structure or ?database.? ta b l e 3 0 summarizes the structure sub- sections and address locations. c.3 block status register the block status register indicates whether an erase operation completed successfully or whether a given block is locked or can be accessed for flash program/erase operations. see ta b l e 3 1 . block erase status (bsr[1]) allows system software to determine the success of the last block erase operation. bsr[1] can be us ed just after power-up to verify that the vcc supply was not accidentally removed during an erase operation. table 29: example of query structure output of x16 devices word addressing: offset hex code value a[x-0] dq[16:0] 0x00010 0051 "q" 0x00011 0052 "r" 0x00012 0059 "y" 0x00013 p_idlo prvendor 0x00014 p_idhi id # 0x00015 plo prvendor 0x00016 phi tbladr 0x00017 a_idlo altvendor 0x00018 a_idhi id # ... ... ... table 30: query structure offset sub-section name description 1 0x00000 manufacturer code 0x00001 device code 0x(ba+2) 2 block status register bloc k-specific information 0x00004-0xf reserved reserved for vendor-specific information 0x00010 cfi query identification string command set id and vendor data offset 0x0001b system interface information device timing & voltage information 0x00027 device geometry defi nition flash device layout p 3 primary numonyx-specific extended query table vendor-defined additional informatio n specific to the primary vendor algorithm notes: 1. refer to the query structure output section and offset 0x28 for the detailed definition of offset address as a function of device bus width and mode. 2. ba = block address beginning location (i.e., 0x08000 is bloc k 1?s beginning location when the block size is 32k-word). 3. offset 15 defines ?p? which points to the pr imary numonyx-specific extended query table.
c3 discrete datasheet march 2008 64 290645-24 notes: 1. ba = block address beginning location (i.e., 0x08000 is bloc k 1?s beginning location when the block size is 32k-word). c.4 cfi query identification string the identification string provides verification that the component supports the common flash interface specification. it also indicates the specification version and supported vendor-specified command set(s). see ta b l e 3 2 . table 31: block status register offset length description add. value 0x(ba+2) 1 1 block lock status register ba+2 --00 or --01 bsr[0] block lock status 0 = unlocked 1 = locked ba+2 (bit 0): 0 or 1 bsr[1] block lock-down status 0 = not locked down 1 = locked down ba+2 (bit 1): 0 or 1 bsr[7:2]: reserved for future use ba+2 (bit 2-7): 0 table 32: cfi identification offset length description add. hex code value 0x10 3 query-unique ascii string ?qry? 10: 11: 12: --51 --52 --59 ?q? ?r? ?y? 0x13 2 primary vendor command set and control interface id code 16-bit id code for vendor-specified algorithms 13: 14: --03 --00 0x15 2 extended query table primary algorithm address 15: 16: --35 --00 0x17 2 alternate vendor command set and control interface id code 0x0000 means no second vendor-specified algorithm exists 17: 18: --00 --00 0x19 2 secondary algorithm extended query table address 0x0000 means none exists 19: 1a: --00 --00 table 33: system interface information offset length description add. hex code value 0x1b 1 v cc logic supply minimum program/erase voltage bits 0?3 bcd 100 mv bits 4?7 bcd volts 1b: --27 2.7 v 0x1c 1 v cc logic supply maximum program/erase voltage bits 0?3 bcd 100 mv bits 4?7 bcd volts 1c: --36 3.6 v 0x1d 1 v pp [programming] supply minimum program/erase voltage bits 0?3 bcd 100 mv bits 4?7 hex volts 1d: --b4 11.4 v 0x1e 1 v pp [programming] supply maxi mum program/erase voltage bits 0?3 bcd 100 mv bits 4?7 hex volts 1e: --c6 12.6 v 0x1f 1 ?n? such that typical single word program time-out =2 n s 1f: --05 32 s
march 2008 datasheet 290645-24 65 c3 discrete c.5 device geometry definition 0x20 1 ?n? such that typical max. buffer write time-out = 2 n s 20: --00 na 0x21 1 ?n? such that typical block erase time-out = 2 n ms 21: --0a 1 s 0x22 1 ?n? such that typical full chip erase time-out = 2 n ms 22: --00 na 0x23 1 ?n? such that maximum word program time-out = 2 n times typical 23: --04 512s 0x24 1 ?n? such that maximu m buffer write time-out = 2 n times typical 24: --00 na 0x25 1 ?n? such that maximum block erase time-out = 2 n times typical 25: --03 8s 0x26 1 ?n? such that maximum chip erase time-out = 2 n times typical 26: --00 na table 33: system interface information offset length description add. hex code value table 34: device geometry definition offset length description add. hex code value 0x27 1 ?n? such that device size = 2 n in number of bytes 27 see ta b l e 3 5 , ?device geometry details? on page 66 0x28 2 flash device interface: x8 async 28:00,29:0 0 x16 async 28:01,29:00 x8/x16 async 28:02,29:00 28: 29: --01 --00 x16 0x2a 2 ?n? such that maximum number of bytes in write buffer = 2 n 2a: 2b: --00 --00 0 0x2c 1 number of erase block regions within device: 1. x = 0 means no erase blocking; the device erases in ?bulk? 2. x specifies the number of device or partition regions with one or more contiguous same-size erase blocks. 3. symmetrically blocked partitions have one blocking region 4. partition size = (total blocks) x (individual block size) 2c: --02 2 0x2d 4 erase block region 1 information bits 0?15 = y, y+1 = number of identical-size erase blocks bits 16?31 = z, region erase block(s) size are z x 256 bytes 2d: 2e: 2f: 30: see ta b l e 3 5 , ?device geometry details? on page 66 0x2d 14 erase block region 2 information bits 0?15 = y, y+1 = number of identical-size erase blocks bits 16?31 = z, region erase block(s) size are z x 256 bytes 31: 32: 33: 34: see ta b l e 3 5 , ?device geometry details? on page 66
c3 discrete datasheet march 2008 66 290645-24 c.6 numonyx-specific extended query table certain flash features and commands are optional as shown in table 36, ?primary- vendor specific extended query? on page 66 . the numonyx - specific extended query table specifies these features as well as other similar types of information. table 35: device geometry details address 16 mbit 32 mbit 64 mbit -b -t -b -t -b -t 0x27 --15 -15 --16 -16 --17 --17 0x28 --01 --01 --01 --01 --01 --01 0x29 --00 --00 --00 -00 -00 -00 0x2a --00 --00 --00 -00 -00 -00 0x2b --00 --00 --00 -00 -00 -00 0x2c --02 --02 --02 --02 --02 --02 0x2d --07 --1e --07 --3e --07 --7e 0x2e --00 --00 --00 -00 -00 -00 0x2f --20 --00 --20 -00 --20 --00 0x30 --00 --01 --00 --01 --00 --01 0x31 --1e --07 --3e --07 --7e --07 0x32 --00 --00 --00 -00 -00 -00 0x33 --00 --20 --00 --20 --00 --20 0x34 --01 --00 --01 --00 --01 --00 table 36: primary-vendor specific extended query (sheet 1 of 2) offset 1 p = 0x15 length description (optional flash features and commands) address hex code value 0x(p+0) 0x(p+1) 0x(p+2) 3 primary extended query table unique ascii string ?pri? 35: 36: 37: --50 --52 --49 ?p? ?r? ?i? 0x(p+3) 1 major version number, ascii 38: --31 ?1? 0x(p+4) 1 minor version number, ascii 39: --30 ?0? 0x(p+5) 0x(p+6) 0x(p+7) 0x(p+8) 4 optional feature and command support (1=yes, 0=no) bits 9?31 are reserved; undefined bits are ?0.? if bit 31 is ?1? then another 31 bit field of optional features follows at the end of the bit-30 field. 3a: 3b: 3c: 3d: --66 --00 --00 --00 bit 0 chip erase supported bit 1 suspend erase supported bit 2 suspend program supported bit 3 legacy lock/unlock supported bit 4 queued erase supported bit 5 instant individual block locking supported bit 6 protection bits supported bit 7 page mode read supported bit 8 synchronous read supported bit 0 = 0 bit 1 = 1 bit 2 = 1 bit 3 = 0 bit 4 = 0 bit 5 = 1 bit 6 = 1 bit 7 = 0 bit 8 = 0 no yes yes no no yes yes no no
march 2008 datasheet 290645-24 67 c3 discrete 0x(p+9) 1 supported functions after suspend: read array, status, query other supported operations are: bits 1?7 reserved; undefined bits are ?0? 3e: --01 bit 0 program supported after erase suspend bit 0 = 1 yes 0x(p+a) 0x(p+b) 2 block status register mask bits 2?15 are reserved; undefined bits are ?0? bit 0 block lock-bit status register active bit 1 block lock-down bit status active 3f: --03 40: --00 bit 0 = 1 yes bit 1 = 1 yes 0x(p+c) 1 v cc logic supply highest performance program/ erase voltage bits 0?3 bcd value in 100 mv bits 4?7 bcd value in volts 41: --33 3.3 v 0x(p+d) 1 v pp optimum program/erase supply voltage bits 0?3 bcd value in 100 mv bits 4?7 hex value in volts 42: --c0 12.0 v notes: 1. the variable p is a pointer whic h is defined at cfi offset 0x15. table 37: protection register information offset 1 p = 0x35 length description (optional flash features and commands) address hex code value 0x(p+e) 1 number of protection register fields in jedec id space. ?00h,? indicates that 256 protection bytes are available 43: --01 01 0x(p+f) 0x(p+10) (0xp+11) 4 44: 45: 46: --80 --00 --03 80h 00h 8 byte 0x(p+12) protection field 1: protection description this field describes user-available one time programmable (otp) protection register bytes. some are pre-programmed with device- unique serial numbers. others are user programmable. bits 0?15 point to the protection register lock byte, the section?s first byte. the following bytes are factory pre-programmed and user- programmable. bits 0?7 = lock/bytes jedec-plane physical low address bits 8?15 = lock/bytes jedec -plane physical high address bits 16?23 = ?n? such that 2 n = factory pre-programmed bytes bits 24?31 = ?n? such that 2 n = user programmable bytes 47: --03 8 byte 0x(p+13) reserved for future use 48: notes: 1. the variable p is a pointer whic h is defined at cfi offset 0x15. table 36: primary-vendor specific extended query (sheet 2 of 2) offset 1 p = 0x15 length description (optional flash features and commands) address hex code value
c3 discrete datasheet march 2008 68 290645-24 appendix d additional information order number document/tool 297938 3 volt advanced+ boot block flash memory specification update 292216 ap-658 designing for upgrade to th e advanced+ boot block flash memory 292215 ap-657 designing with the advanced+ boot block flash memory architecture contact your numonyx representative numonyx? flash data integrator (numonyx? fdi) software developer?s kit 297874 ifdi interactive: play with numonyx? flash data integrator on your pc notes: 1. to request numonyx documentation or tools, contact your local numonyx or distribution sales office.
march 2008 datasheet 290645-24 69 c3 discrete appendix e ordering information figure 23: component ordering information package te = 48- lead tsop gt = 48- ball bga * csp ge = vf bga csp rc = easy bga pc = pb free easy bga ph = pb free vfbga js = pb free tsop product line designator for all intel ? flash products access speed (ns) (70, 80 , 90, 100 , 110 ) product family c3 = 3 volt advanced+ boot block v cc = 2.7 v?3.6 v v pp = 2.7 v?3.6 v or 11 .4 v?12.6 v device density 640 = x16 (64 mbit) 320 = x16 (32 mbit) 160 = x16 (16 mbit) 800 = x16 (8 mbit) t = top blocking b = bottom blocking lithography a = 0.25 m c = 0.18 m d = 0.13 m t e 2 8 f 3 2 0 c 3 t c 7 0
c3 discrete datasheet march 2008 70 290645-24 table 38: product information ordering matrix valid combinations (all extended temperature) 48-lead tsop 48-ball bga* csp 48-ball vf bga easy bga extended 64 mbit extended 32 mbit te28f320c3td70 te28f320c3bd70 te28f320c3tc70 te28f320c3bc70 te28f320c3tc90 te28f320c3bc90 te28f320c3ta100 te28f320c3ba100 te28f320c3ta110 te28f320c3ba110 js28f320c3bd70 js28f320c3td70 js28f320c3bd90 js28f320c3td90 gt28f320c3ta100 gt28f320c3ba100 gt28f320c3ta110 gt28f320c3ba110 ge28f320c3td70 ge28f320c3bd70 ge28f320c3tc70 GE28F320C3BC70 ge28f320c3tc90 ge28f320c3bc90 ph28f320c3bd70 ph28f320c3td70 ph28f320c3bd90 ph28f320c3td90 rc28f320c3td70 rc28f320c3bd70 rc28f320c3td90 rc28f320c3bd90 rc28f320c3tc90 rc28f320c3bc90 rc28f320c3ta100 rc28f320c3ba100 rc28f320c3ta110 rc28f320c3ba110 pc28f320c3bd70 pc28f320c3td70 pc28f320c3bd90 pc28f320c3td90 extended 16 mbit te28f160c3td70 te28f160c3bd70 te28f160c3tc70 te28f160c3bc70 te28f160c3tc80 te28f160c3bc80 te28f160c3tc90 te28f160c3bc90 te28f160c3ta90 te28f160c3ba90 te28f160c3ta110 te28f160c3ba110 js28f160c3bd70 js28f160c3td70 gt28f160c3ta90 gt28f160c3ba90 gt28f160c3ta110 gt28f160c3ba110 ge28f160c3td70 ge28f160c3bd70 ge28f160c3tc70 ge28f160c3bc70 ge28f160c3tc80 ge28f160c3bc80 ge28f160c3tc90 ge28f160c3bc90 ph28f160c3bd70 ph28f160c3td70 rc28f160c3td70 rc28f160c3bd70 rc28f160c3tc70 rc28f160c3bc70 rc28f160c3tc80 rc28f160c3bc80 rc28f160c3tc90 rc28f160c3bc90 rc28f160c3ta90 rc28f160c3ba90 rc28f160c3ta110 rc28f160c3ba110 pc28f160c3bd70 pc28f160c3td70 extended 8 mbit te28f800c3td70 te28f800c3bd70 te28f800c3ta90 te28f800c3ba90 te28f800c3ta110 te28f800c3ba110 js28f800c3bd70 js28f800c3td70 rc28f800c3td70 rc28f800c3bd70 rc28f800c3ta90 rc28f800c3ba90 rc28f800c3ta110 rc28f800c3ba110 pc28f800c3bd70 pc28f800c3td70 note: the second line of the 48-ball bga package top side mark specifies assembly codes. for samples only, the first character signifies either ?e? for engineering samples or ?s ? for silicon daisy chain sample s. all other a ssembly codes without an ?e? or ?s? as the first character are production units.

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